ML4841
FUNCTIONAL DESCRIPTION (Continued)
At V = 13.5V and assuming Ramp Peak = 5V to allow
PWM Control (RAMP 2)
CC
for component tolerances:
The PWM section utilizes current mode control. RAMP 2
is generally used as the sampling point for a voltage
representing the current in the primary of the PWM’s
output transformer, derived either by a current sensing
resistor or a current transformer.
(9)
t
= 0.463×R × C
T T
CHARGE
The capacitor value should remain small to keep the
discharge energy and the resulting discharge current
through the part small. A good value to use is the same
Soft Start
value used in the PWM timing circuit (C ).
T
Start-up of the PWM is controlled by the selection of the
external capacitor at SS. A current source of 50µA supplies
the charging current for the capacitor, and start-up of the
PWM begins at 1.25V. Start-up delay can be programmed
by the following equation:
For the application circuit shown in the data sheet, using a
200kHz PWM and 390pF timing cap yields R :
T
1×10−5
(0.463)(390 ×10−12
RT =
= 56.2kΩ
(10)
)
50µA
C
SS
= t
×
(11)
DELAY
1.25V
where C is the required soft start capacitance, and
DELAY
SS
PWM SECTION
t
is the desired start-up delay.
Pulse Width Modulator
It is important that the time constant of the PWM soft-start
allows the PFC time to generate sufficient output power
for the PWM section. The PWM start-up delay should be
at least 5ms.
The PWM section of the ML4841 is straightforward, but
there are several points which should be noted. Foremost
among these is its inherent synchronization to the PFC
section of the device, to which it also provides its basic
timing. The PWM operates in current-mode. In
Solving for the minimum value of C :
SS
applications utilizing current mode control, the PWM
ramp (RAMP 2) is usually derived directly from a current
sensing resistor or current transformer in the primary of
the output stage, and is thereby representative of the
current flowing in the converter’s output stage. The DC
50µA
1.25V
CSS = 5ms ×
= 200nF
I
comparator provides cycle-by-cycle current limiting
LIMIT
and is connected to RAMP 2 internally. If the current sense
signal exceeds the 1V threshold, the PWM switch is
disabled until the protection flip-flop is rest by the clock
pulse at the start of the next PWM power cycle.
V
BIAS
PWM Current Limit
The DC I
comparator is a cycle-by-cycle current
LIMIT
limiter for the PWM section. Should the input voltage at
this pin ever exceed 1V, the output of the PWM will be
disabled until the output flip-flop is reset by the clock
pulse at the start of the next PWM power cycle.
V
CC
10nF
ceramic
1µF
ceramic
ML4841
GND
V
OK Comparator
IN
The V OK comparator monitors the DC output of the
IN
PFC and inhibits the PWM if this voltage on V is less
FB
than its nominal 2.5V. Once this voltage reaches 2.5V,
which corresponds to the PFC output capacitor being
charged to its rated boost voltage, the soft-start
commences.
Figure 3. External Component Connections to V
CC
10
MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
