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ML4833CP 参数 Datasheet PDF下载

ML4833CP图片预览
型号: ML4833CP
PDF下载: 下载PDF文件 查看货源
内容描述: 电子调光镇流器控制器 [Electronic Dimming Ballast Controller]
分类和应用: 光电二极管信息通信管理电子控制器
文件页数/大小: 13 页 / 272 K
品牌: MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
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ML4833
FUNCTIONAL DESCRIPTION
OVERVIEW
The ML4833 consists of peak current controlled
continuous boost power factor front end section with a
flexible ballast control section. Start-up and lamp-out
retry timing are controlled by the selection of external
timing components, allowing for control of a wide variety
of different lamp types. The ballast section controls the
lamp power using frequency modulation (FM) with
additional programmability provided to adjust the VCO
frequency range. This allows for the IC to be used with a
variety of different output networks. Figure 1 depicts a
detailed block diagram of ML4833.
POWER FACTOR SECTION
The ML4833 power factor section is a peak current
sensing boost mode PFC control circuit in which only
voltage loop compensation is needed. It is simpler than a
conventional average current control method. It consists
of a voltage error amplifier, a current sense amplifier (no
compensation is needed), an integrator, a comparator, and
a logic control block. In the boost topology, power factor
correction is achieved by sensing the output voltage and
the current flowing through the current sense resistor. Duty
cycle control is achieved by comparing the integrated
voltage signal of the error amplifier and the voltage
across R
SENSE
. The duty cycle control timing is shown in
Figure 2. Setting minimum input voltage for output
regulation can be achieved by selecting C
RAMP
according
to equation 1.
C
RAMP
=
PEAO
MAX
1
(1
D)Ts
1.1
µ
s
22K
2P
V
OUT
2V
IN
OUT
(1
D)Ts
8R
SENSE
2L
V
IN
{
}
(1)
OVERVOLTAGE PROTECTION AND INHIBIT
The OVP pin serves to protect the power circuit from
being subjected to excessive voltages if the load should
change suddenly (lamp removal). A divider from the high
voltage DC bus sets the OVP trip level. When the voltage
on PVFB/OVP exceeds 2.75V, the PFC transistor are
inhibited. The ballast section will continue to operate.
6
7
R
SET
R
T
/C
T
OSC
CLK
+
+
+
S
2.5V
+
V TO I
+
R
Q
1.25V
LFB OUT
2.5V
LAMP FB
INTERRUPT
PDWN
5
9
R
X
/C
X
4
8
3
PREHEAT
TIMER
16
17
11
VCC
V
REF
GND
UNDER-VOLTAGE
THERMAL SHUTDOWN
REFOK
1.0V
18
1
10
PVFB/OVP
PEAO
C
RAMP
PFC OUT
2.75V
+
OVP
S
R
T Q
–1.0V
+
2
PIFB
ILIM
OUT B
PGND
I
SENSE
AMPLIFIER
Q
OUT A
15
14
13
12
Figure 1. ML4833 Detailed Block Diagram
6