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ML4826IS-2 参数 Datasheet PDF下载

ML4826IS-2图片预览
型号: ML4826IS-2
PDF下载: 下载PDF文件 查看货源
内容描述: PFC和双输出PWM控制器组合 [PFC and Dual Output PWM Controller Combo]
分类和应用: 功率因数校正控制器
文件页数/大小: 16 页 / 299 K
品牌: MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
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ML4826  
FUNCTIONAL DESCRIPTION (Continued)  
current source. The circuit guarantees that the maximum  
operating current is available at all times and minimizes  
the worst case power dissipation in the IC.  
trailing edge modulation is determined during the ON  
time of the switch. Figure 4 shows a typical trailing edge  
control scheme.  
Other methods such as a simple series resistor are  
In the case of leading edge modulation, the switch is  
turned OFF right at the leading edge of the system clock.  
When the modulating ramp reaches the level of the error  
amplifier output voltage, the switch will be turned ON.  
The effective duty-cycle of the leading edge modulation is  
determined during the OFF time of the switch. Figure 5  
shows a leading edge control scheme.  
possible, but can very easily lead to excessive I current  
CC  
in the ML4826. Figures 6 and 7 show other possible  
methods for feeding V  
.
CC  
LEADING/TRAILING MODULATION  
Conventional Pulse Width Modulation (PWM) techniques  
employ trailing edge modulation in which the switch will  
turn on right after the trailing edge of the system clock. The  
error amplifier output voltage is then compared with the  
modulating ramp. When the modulating ramp reaches the  
level of the error amplifier output voltage, the switch will  
be turned OFF. When the switch is ON, the inductor  
current will ramp up. The effective duty cycle of the  
One of the advantages of this control technique is that it  
requires only one system clock. Switch 1 (SW1) turns off  
and switch 2 (SW2) turns on at the same instant to  
minimize the momentary “no-load” period, thus lowering  
ripple voltage generated by the switching action. With  
such synchronized switching, the ripple voltage of the first  
stage is reduced. Calculation and evaluation have shown  
that the 120Hz component of the PFC’s output ripple  
voltage can be reduced by as much as 30% using this  
method.  
V
BIAS  
RECTIFIED  
V
AC  
20V  
V
CC  
22kΩ  
1µF  
ML4826  
T1  
Q2  
MJE200  
39kΩ  
RTN  
Q1  
2N2222  
18Ω  
Figure 6.  
1500µF  
V
BIAS  
V
CC  
GATE  
DRIVE  
ML4826  
1µF  
RTN  
V
CC  
Figure 5. V Bias Circuitry  
CC  
ML4826  
RTN  
Figure 7.  
12