ML4805
FUNCTIONAL DESCRIPTION (Continued)
LEADING/TRAILING MODULATION
Generating V
Conventional Pulse Width Modulation (PWM) techniques
employ trailing edge modulation in which the switch will
turn on right after the trailing edge of the system clock.
The error amplifier output voltage is then compared with
the modulating ramp. When the modulating ramp reaches
the level of the error amplifier output voltage, the switch
will be turned OFF. When the switch is ON, the inductor
current will ramp up. The effective duty cycle of the
trailing edge modulation is determined during the ON
time of the switch. Figure 3 shows a typical trailing edge
control scheme.
CC
The ML4805 is a voltage-fed part. It requires an external
15V±10% or better Zener shunt voltage regulator, or some
other controlled supply, to regulate the voltage supplied
to the part at 15V nominal. This allows a low power
dissipation while at the same time delivering 13V
nominal of gate drive at the PWM OUT and PFC OUT
outputs. If using a Zener diode, it is important to limit the
current through the Zener to avoid overheating or
destroying it. This can be easily done with a single resistor
in series with the Vcc pin, returned to a bias supply of
typically 18V to 20V. The resistor’s value must be chosen
to meet the operating current requirement of the ML4805
itself (8.5mA max.) plus the current required by the two
gate driver outputs.
In the case of leading edge modulation, the switch is
turned OFF right at the leading edge of the system clock.
When the modulating ramp reaches the level of the error
amplifier output voltage, the switch will be turned ON.
The effective duty-cycle of the leading edge modulation
is determined during the OFF time of the switch. Figure 4
shows a leading edge control scheme.
EXAMPLE:
With a V
of 20V, a V limit of 16.5V (max) and
CC
BIAS
driving a total gate charge of 110nC at 100kHz (1 IRF840
MOSFET and 2 IRF830 MOSFETs), the gate driver current
required is:
One of the advantages of this control technique is that it
requires only one system clock. Switch 1 (SW1) turns off
and switch 2 (SW2) turns on at the same instant to
minimize the momentary “no-load” period, thus lowering
ripple voltage generated by the switching action. With
such synchronized switching, the ripple voltage of the
first stage is reduced. Calculation and evaluation have
shown that the 120Hz component of the PFC’s output
ripple voltage can be reduced by as much as 30% using
this method.
IGATEDRIVE = 100kHz ´ 110nC = 11mA
20V - 16.5V
RBIAS
=
= 180Ω
7.5mA + 11mA
The ML4805 should be locally bypassed with a 10nF and
a 1µF ceramic capacitor. In most applications, an
electrolytic capacitor of between 100µF and 330µF is also
required across the part, both for filtering and as part of
the start-up bootstrap circuitry.
SW2
SW1
I2
I3
I4
SW2
SW1
I2
I3
I4
L1
I1
L1
I1
+
+
VIN
RL
VIN
RL
DC
DC
RAMP
RAMP
C1
C1
VEAO
VEAO
REF
U3
EA
U3
EA
+
–
+
–
REF
VEAO
TIME
TIME
DFF
DFF
U2
CMP
VSW1
VSW1
+
–
+
–
R
RAMP
CLK
Q
Q
R
D
RAMP
CLK
Q
U1
U1
OSC
U4
D
OSC
U4
U2
Q
CLK
CLK
TIME
TIME
Figure 3. Typical Trailing Edge Control Scheme
Figure 4. Leading/Trailing Edge Control Scheme
10
MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
