ML4803
TYPICAL APPLICATIONS
(Continued)
offset voltage to the current sense signal, which forces the
duty cycle to zero at light loads. This offset prevents the
PFC from operating in the DCM and forces pulse-skipping
from CCM to no-duty, avoiding DMC operation. External
filtering to the current sense signal helps to smooth out
the sense signal, expanding the operating range slightly
into the DCM range, but this should be done carefully, as
this filtering also reduces the bandwidth of the signal
feeding the pulse-by-pulse current limit signal. Figure 9
displays a typical circuit for adding offset to I
SENSE
at
light loads.
PFC Start-Up and Soft Start
During steady state operation VEAO draws 35µA. At start-
up the internal current mirror which sinks this current is
defeated until V
CC
reaches 12V. This forces the PFC error
voltage to V
CC
at the time that the IC is enabled. With
leading edge modulation V
CC
on the VEAO pin forces
zero duty on the PFC output. When selecting external
compensation components and V
CC
supply circuits VEAO
must not be prevented from reaching 6V prior to V
CC
reaching 12V in the turn-on sequence. This will guarantee
that the PFC stage will enter soft-start. Once V
CC
reaches
12V the 35µA VEAO current sink is enabled. VEAO
compensation components are then discharged by way of
the 35µA current sink until the steady state operating point
is reached. See Figure 8.
PFC SOFT RECOVERY FOLLOWING V
CC
OVP
The ML4803 assumes that V
CC
is generated from a source
that is proportional to the PFC output voltage. Once that
source reaches 16.2V the internal current sink tied to the
VEAO pin is disabled just as in the soft start turn-on
sequence. Once disabled, the VEAO pin charges HIGH
by way of the external components until the PFC duty
cycle goes to zero, disabling the PFC. The V
CC
OVP resets
once the VCC discharges below 16.2V, enabling the
Once V
CC
reaches 12V both the PFC and PWM are
enabled. The UVLO threshold is 9.1V providing 2.9V of
hysteresis.
GENERATING V
CC
An internal clamp limits overvoltage to V
CC
. This clamp
circuit ensures that the V
CC
OVP circuitry of the ML4803
will function properly over tolerance and temperature
while protecting the part from voltage transients. This
circuit allows the ML4803 to deliver 15V nominal gate
drive at PWM OUT and PFC OUT, sufficient to drive low-
cost IGBTs.
It is important to limit the current through the Zener to
avoid overheating or destroying it. This can be done with
a single resistor in series with the V
CC
pin, returned to a
bias supply of typically 14V to 18V. The resistor value
must be chosen to meet the operating current requirement
of the ML4803 itself (4.0mA max) plus the current
required by the two gate driver outputs.
V
CC
OVP
V
CC
is assumed to be a voltage proportional to the PFC
output voltage, typically a bootstrap winding off the boost
VEAO current sink and discharging the VEAO
compensation components until the steady state operating
point is reached. It should be noted that, as shown in
Figure 8, once the VEAO pin exceeds 6.5V, the internal
ramp is defeated. Because of this, an external Zener can
be installed to reduce the maximum voltage to which the
VEAO pin may rise in a shutdown condition. Clamping
the VEAO pin externally to 7.4V will reduce the time
required for the VEAO pin to recover to its steady state
value.
UVLO
VCC
0
VEAO
0
VOUT
0
10V/div.
C23
0.01µF
10V/div.
R29
20kΩ
R28
20kΩ
R4
1kΩ
PFC
GATE
CR16
1N4148
C16
1µF
R19
10kΩ
ISENSE
C5
0.0082µF
10V/div.
R3
0.015Ω
3W
VBOOST
0
200ms/Div.
200V/div.
VCC
RTN
Figure 8. PFC Soft Start
Figure 9. I
SENSE
Offset for Light Load Conditions
February 1999
9
MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
