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ML4803CP-2 参数 Datasheet PDF下载

ML4803CP-2图片预览
型号: ML4803CP-2
PDF下载: 下载PDF文件 查看货源
内容描述: 8引脚PFC和PWM控制器组合 [8-Pin PFC and PWM Controller Combo]
分类和应用: 功率因数校正光电二极管信息通信管理控制器
文件页数/大小: 13 页 / 185 K
品牌: MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
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ML4803  
TYPICAL APPLICATIONS (Continued)  
1
to develop the internal ramp by charging the internal  
30pF +12/10% capacitor. See Figures 10 and 11. The  
frequency of the internal programming ramp is set  
internally to 67kHz.  
RCOMP  
(3)  
(4)  
2
f
CCOMP  
1
RCOMP  
330k  
6.28 30Hz 16nF  
PFC CURRENT SENSE FILTERING  
1
f
CZERO  
In DCM, the input current wave shaping technique used  
by the ML4803 could cause the input current to run away.  
In order for this technique to be able to operate properly  
under DCM, the programming ramp must meet the boost  
inductor current down-slope at zero amps. Assuming the  
programming ramp is zero under light load, the OFF-time  
will be terminated once the inductor current reaches zero.  
Subsequently the PFC gate drive is initiated, eliminating  
the necessary dead time needed for the DCM mode. This  
2
RCOMP  
10  
1
CZERO  
0.16 F  
6.28 3Hz 330k  
INTERNALVOLTAGE RAMP  
The internal ramp current source is programmed by way of  
the VEAO pin voltage. Figure 7 displays the internal ramp  
current vs. the VEAO voltage. This current source is used  
forces the output to run away until the V OVP shuts  
CC  
down the PFC. This situation is corrected by adding an  
60  
Power Stage  
Overall Gain  
Compensation  
Network Gain  
40  
20  
V
O
0
11.3M  
VEAO  
ML4803  
I
ML4803  
OUT  
20  
40  
60  
R
667Ω  
LOAD  
220µF  
330kΩ  
15nF  
I
VEAO  
35µA  
V  
+
EAO  
0.15µF  
0.1  
1
10  
100  
1000  
POWER  
STAGE  
COMPENSATION  
FREQUENCY (Hz)  
Figure 4. Voltage Control Loop  
Figure 5. Voltage Loop Gain  
50  
40  
30  
20  
10  
0
0
50  
Power Stage  
Overall  
Compensation  
Network  
FF @ 55ºC  
TYP @ 55ºC  
TYP @ ROOM TEMP  
TYP @ 155ºC  
SS @ 155ºC  
100  
150  
200  
0
1
2
3
4
5
6
7
0.1  
1
10  
100  
1000  
V
(V)  
FREQUENCY (Hz)  
EAO  
Figure 6. Voltage Loop Phase  
Figure 7. Internal Ramp Current vs. V  
EAO  
8
February 1999