ML4803
FUNCTIONAL DESCRIPTION
The ML4803 consists of an average current mode boost
Power Factor Corrector (PFC) front end followed by a
synchronized Pulse Width Modulation (PWM) controller. It
is distinguished from earlier combo controllers by its low
pin count, innovative input current shaping technique, and
very low start-up and operating currents. The PWM section
is dedicated to peak current mode operation. It uses
conventional trailing-edge modulation, while the PFC uses
leading-edge modulation. This patented Leading Edge/
Trailing Edge (LETE) modulation technique helps to
minimize ripple current in the PFC DC buss capacitor.
is offset internally by 1.2V and then compared against the
opto feedback voltage to set the PWM duty cycle.
PFC OUT and PWM OUT
PFC OUT and PWM OUT are the high-current power
drivers capable of directly driving the gate of a power
MOSFET with peak currents up to ±1A. Both outputs are
actively held low when V is below the UVLO threshold
CC
level.
V
CC
The ML4803 is offered in two versions. The ML4803-1
operates both PFC and PWM sections at 67kHz, while the
ML4803-2 operates the PWM section at twice the
frequency (134kHz) of the PFC. This allows the use of
smaller PWM magnetics and output filter components,
while minimizing switching losses in the PFC stage.
V
is the power input connection to the IC. The V start-
CC
CC
up current is 150µA . The no-load I current is 2mA. V
quiescent current will include both the IC biasing currents
and the PFC and PWM output currents. Given the
operating frequency and the MOSFET gate charge (Qg),
average PFC and PWM output currents can be calculated
CC
CC
In addition to power factor correction, several protection
features have been built into the ML4803. These include
soft start, redundant PFC over-voltage protection, peak
current limiting, duty cycle limit, and under voltage
lockout (UVLO). See Figure 12 for a typical application.
as I
= Qg x F. The average magnetizing current
OUT
required for any gate drive transformers must also be
included. The V pin is also assumed to be proportional
to the PFC output voltage. Internally it is tied to the
CC
V
OVP comparator (16.2V) providing redundant high-
CC
speed over-voltage protection (OVP) of the PFC stage.
V also ties internally to the UVLO circuitry, enabling
CC
DETAILED PIN DESCRIPTIONS
the IC at 12V and disabling it at 9.1V. V must be
CC
V
bypassed with a high quality ceramic bypass capacitor
placed as close as possible to the IC.
Good bypassing is critical to the proper operation of the
ML4803.
EAO
This pin provides the feedback path which forces the PFC
output to regulate at the programmed value. It connects to
programming resistors tied to the PFC output voltage and
is shunted by the feedback compensation network.
V
CC
is typically produced by an additional winding off
the boost inductor or PFC Choke, providing a voltage that
is proportional to the PFC output voltage. Since the
I
SENSE
V
OVP max voltage is 16.2V, an internal shunt limits
overvoltage to an acceptable value. An external
CC
This pin ties to a resistor or current sense transformer
which senses the PFC input current. This signal should be
negative with respect to the IC ground. It internally feeds
the pulse-by-pulse current limit comparator and the
V
CC
clamp, such as shown in Figure 1, is desirable but not
necessary.
current sense feedback signal. The I
trip level is –1V.
V
is internally clamped to 16.7V minimum, 18.3V
LIMIT
CC
The I
feedback is internally multiplied by a gain of
maximum. This limits the maximum V that can be
SENSE
CC
four and compared against the internal programmed ramp
to set the PFC duty cycle. The intersection of the boost
inductor current downslope with the internal
applied to the IC while allowing a V which is high
CC
programming ramp determines the boost off-time.
V
CC
V
DC
1N4148
1N4148
This pin is typically tied to the feedback opto-collector. It
is tied to the internal 5V reference through a 26kW resistor
and to GND through a 40kW resistor.
I
LIMIT
1N5246B
This pin is tied to the primary side PWM current sense
resistor or transformer. It provides the internal pulse-by
pulse-current limit for the PWM stage (which occurs at
1.5V) and the peak current mode feedback path for the
current mode control of the PWM stage. The current ramp
GND
Figure 1. Optional V Clamp
CC
February 1999
5
MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
