PRELIMINARY
ML4435
FUNCTIONAL DESCRIPTION
times the commutation frequency. The TACH out also
indicates a low motor speed by staying TTL high when the
motor is at its minimum speed (SPEED FB below 0.97V).
The back EMF sampler takes the motor phase voltages
divided down to signals that are less than VCC (12V
nominal) and calculates the neutral point of the motor by
the following equation:
BACK EMF SAMPLER
The input to the VCO (pin 18) SPEED FB is controlled by
the Back EMF Sampler. The back EMF sense pins FB A,
FB B, and FB C inputs to the back EMF sampler require
a signal from the motor phase leads that is below the
VCC of the ML4435. The phase sense input impedance is
8.7kΩ. If the motor voltage is greater than the VCC of the
ML4435 then this requires a series resistor RFB from the
motor phase lead shown in Figure 8. RFB can be selected
by using the graph in Figure 9 or using the following
equation:
VNEUTRAL = (FB A + FB B + FB C)/3
This allows the ML4435 to compare the back EMF signal
to the motors neutral point without the need for bringing
out an extra wire on a WYE wound motor. For DELTA
wound motors there isn’t a physical neutral to bring out so
this reference point must be calculated anyway.
The back EMF sampler takes the motor phase that is not
driven (i.e. if LA and HB are on then phase A is driven
low and phase B is driven high then phase C is sampled).
The sampled phase provides a back EMF signal that is
compared against the neutral of the motor. The sampler
is controlled by the commutation state machine. The
sampled back EMF is compared to the neutral through an
error amplifier. The output of the error amplifier outputs
a charging or discharging current to SPEED FB (pin 18)
which provides the voltage to the VCO.
VMOTOR
12
RFB = 8.7kW(
-1)
BLDC
MOTOR
RFBA
RFBB
RFBC
BACK EMF SENSING PHASE LOCKED LOOP
COMMUTATION CONTROL
FBA
4
The three blocks: The commutation state machine, the
VCO, and the back EMF sampler form a phase locked
loop that locks the commutation clock onto the back EMF
signal. The complete phase locked loop is illustrated in
Figure 10. The phased locked loop requires a lead lag
filter that is set by external components on SPEED FB (pin
18). The filter components in Figure 10 work for most
applications. If performance is unstable C1 and C2 can
go up or down a decade in value as low as the C2 stays
equal to C1 x 10.
FBB
5
6 FBC
A
B
C
Figure 8. Back EMF Sampler Configuration
2,000
0,000
FBA
4
FBB
SPEED FB
BACK EMF
SAMPLER
5
RSFB
CSFB
RSFB2
,000
FBC
6
VCO
CSFB2
6,000
4,000
2,000
0
COMMUTATION
STATE MACHINE
0
5
25
V
30
20
Motor Volta e [Max]
Figure 9. RFB vs. VMOTOR [MAX]
Figure 10. Phase Locked Loop
8
PRELIMINARY DATASHEET
May, 2000
MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
