ML2722
7
TPC/TPQ
O (Open
Drain)
Transmit power control output. This
open-drain output is pulled low when the
TPC bit in serial register #0 is set.
Transitions on TPC are synchronized to
the falling edge of RXON. In analog test
modes, this pin and the RSSI output
become test access points controlled by
the serial control bus.
TPQ
MUX
VDD
31
TPC
TPC
MUX
TPC/TPQ
7
100
Ω
8
8
VSS
VSS
VCC5
24
9
REF
I
Input for the 12.288MHz or 6.144MHz
reference frequency. This input is used
as the reference frequency for the PLL
and as a calibration frequency for the on-
chip filters. This is a self-biased CMOS
input that is designed to be driven either
by an AC-coupled sine wave.
9
40k
REF
40k
8
VSS
RVCC1
10
VCC5
11
QPO
O
Charge Pump Output of the phase
detector. This is connected to the
external PLL loop filter.
24
QPO
11
8
VSS
DS2722-F-06
FINAL DATASHEET
DECEMBER 2005 11
MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
