ML2721
PRELIMINARY
FUNCTIONAL DESCRIPTION
INTRODUCTION
CIRCUIT BLOCK DESCRIPTIONS
The ML2721 enables the design and manufacture of low
cost, high performance digital DSSS cordless telephone
transceivers. It can also be used as a general purpose
900MHz transceiver. Integral to the ML2721 is a low IF
receiver whose LO port is driven from an internal
synthesizer. Included are image rejection IF filters,
limiters, discriminator, data slicers, and baseband lowpass
data filters. It also contains internal voltage regulators to
protect critical circuits from power supply noise and
transmit modulation circuits.
PHASE LOCKED LOOP (PLL) AND VOLTAGE
CONTROLLED OSCILLATOR (VCO)
The PLL synthesizes channel frequencies to a 512kHz
resolution, which is more finely spaced than the
1.536MHz signal bandwidth. Non-overlapping channels
are spaced by 2.048MHz where the IF filter and image
reject mixer give a typical adjacent channel rejection of
25dB. There are twelve non-overlapping channels in the
902 to 928MHz ISM band. See Table 1.
The ML2721 has an internal control interface that
programs the synthesizer, the mode of operation, the
external LNA and PA, and provides a convenient and
flexible interface to various baseband processors. For
power level monitoring an RSSI block is included.
Channel
Frequency in MHz
903.680
905.728
907.776
909.824
911.872
913.920
915.968
918.016
920.064
922.112
924.160
926.208
1
2
3
The ML2721 is designed to transmit and receive
1.536Mchips signals in 2.048MHz spaced channels in the
902 to 928MHz ISM band. The 1.536Mchips rate with a
15 bit spreading code gives a 102.4kb/s data rate and
provides a 10dB processing gain.
4
5
6
7
In the Receive mode the ML2721 is a single conversion
low IF receiver. The IF frequency of 1.024MHz results in
an image response in an adjacent channel. An image
reject mixer gives sufficient rejection in this channel. All
IF filtering and demodulation is performed using active
filtering, centered at 1.024MHz. The demodulator is
followed by a matched bit rate filter and a data slicer. The
sliced data is provided to a baseband chip for de-
spreading.
8
9
10
11
12
Table 1. Non-Overlapping Channel Frequencies
In the Transmit mode the ML2721 uses the Receive mode
VCO and frequency division, with a driver amplifier
providing typically 0dBm output to feed the power
amplifier. The PLL frequency synthesizer loop is opened
during the transmit slot, and the VCO is directly
modulated by low-pass filtered circuits from the internal
modulation filter.
The LO PLL is programmed via a 3-wire serial control bus.
Program words are clocked in on the DATA line (pin 5) by
the CLK (pin 6), and loaded into the dividers or control
circuits when EN (pin 4) is asserted. There is no check for
error in the program words. Once loaded, register contents
are preserved regardless of power conditions. The register
status and operation is independent of the mode of
operation of the PLL.
The frequency generation circuits are an internal VCO at
1.83GHz, dividers, a phase comparator and a charge
pump for a PLL frequency synthesizer. The VCO output is
divided by two to produce accurate quadrature outputs at
915MHz. No external components are need for the VCO.
The reference signal from an external crystal oscillator at
either 6.144MHz or 12.288MHz is fed to a programmable
reference divider. The 1.024MHz reference divider output
is fed to the LO phase frequency detector. The PLL
prescaler input comes from the VCO at 1.83GHz, so the
1.024MHz comparison frequency gives 512kHz frequency
resolution at 902 to 928MHz.
Other modes that are available include power down, and
receive and transmit calibrate, which are discussed in
further detail.
The output of the LO divider is fed to the LO phase/
frequency detector and subsequently to the charge pump.
The dividers and charge pump are disabled during the
active slot to save power.
8
January, 2000
PRELIMINARY DATASHEET
MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
