PRELIMINARY
PIN DESCRIPTIONS (continued)
Pin #
3
ML2721
Signal Name
PLLEN
I/O
I (CMOS)
Description
Enables the PLL at the beginning of a Transmit or Receive slot. Goes
low before data is received or transmitted. RXON and PLLEN define
four distinct operating modes. This is a CMOS input, and the thresholds
are referenced to VDD & VSS
The Lock Detect output is an open drain output that goes low when the
PLL is in frequency lock. In analog test modes this pin and the RSSI
output become test access points controlled by the serial control bus
Input for the 6.144MHz or 12.288MHz reference frequency. This is
used as the reference frequency for the PLL, and as a calibration
frequency for the on chip filters. This is a self-biased CMOS input that
is designed to be driven either by a an AC coupled sine wave source
(recommended coupling capacitor is 470pF) or by a standard CMOS
output
Charge Pump Output of the phase detector. This is connected to the
external PLL loop filter
VCO Tuning Voltage input from the PLL loop filter. This pin is very
sensitive to noise coupling and leakage currents
Bandgap reference voltage. Decoupled to ground with a 220nF
capacitor
Buffered Analog RSSI output with a nominal sensitivity of 33mV/dB.
An RF input signal range of –95 to –15dBm gives an RSSI voltage
output of zero to 2.7V. In analog test modes this pin and the LD output
become test access ports
Mode Control and Interface Lines
(Continued)
7
LD/TPQ
O (CMOS)
9
REF
I
11
15
26
28
QPO
VTUNE
VBG
RSSI/TPI
O
I
O
O
Serial Bus Signals
4
EN
I (CMOS)
Enable pin for the three wire serial control bus which sets the
operating frequency and programmable options. The control registers
are loaded on a low to high transition of the signal. Serial control bus
data is ignored when it is high. This is a CMOS input, and the
thresholds are referenced to VDD & VSS
Serial control bus data. 16 bit words which include programming data
and the two bit address of a control register. This is a CMOS input, and
the thresholds are referenced to VDD & VSS
Serial control bus data is clocked in on the rising edge when EN is
low. This is a CMOS input, the thresholds are referenced to VDD & VSS
5
DATA
I (CMOS)
6
CLK
I (CMOS)
January, 2000
PRELIMINARY DATASHEET
7
MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
