ML2037
FUNCTIONAL DESCRIPTION (Continued)
microprocessor crystals meet the above requirements, but
it is recommended to test the selected crystal in circuit to
insure proper operation. Suitable crystals can be
purchased from the following suppliers:
SYNCHRONIZATION
When the SYNC pin is held high, the sine wave generator
operates normally. Pulling this pin low causes the sine
wave output to be interrupted and resets the phase back
to zero. The sine wave output goes to the 2.5V DC level
approximately 1µs after the SYNC input goes low.
Switching the SYNC pin back to a high level starts the
sine wave going again from zero phase. The delay from
when the SYNC goes high to the start of the sine wave is
about 500ns, as shown in Figure 2. If several generator
chips are driven from the same clock, the SYNC input
allows them to be phase synchronized to any value.
Figure 3 gives an example of how a microcontroller can
be used with two ML2037s to generate two sine waves
that are 90º out of phase.
ECS, Inc.
FOX Electronics
M-TRON Industries
An external clock can drive CLK IN directly if desired.
The frequency of this clock can be anything from 0 to
32MHz. However, at clock frequencies below 5MHz, the
sine wave output begins to exhibit "staircasing".
The ML2037 has a clock output that can be used to drive
other external devices. The CLK OUT output is a buffered
output from the oscillator which runs at one half the
frequency of CLK IN.
SHUTDOWN
The SHDN input provides a means to power down the
analog section and the internal clock of the sine wave
generator. When in the power down mode the part will
draw only 10µA of input current and the output will go to
zero approximately 500ns after the SHDN pin goes high.
Switching the SHDN back to a low level allows the sine
wave to resume at the last programmed frequency. The
delay from when the SHDN goes low to when the sine
wave resumes is about 200µs. The use of the power down
mode allows power management for portable applications
or for gating the internal oscillator for low noise
applications.
SERIAL DIGITAL INTERFACE
The digital interface consists of a shift register and data
latch. The serial 16-bit data word on S DATA IN is clocked
into a 16-bit shift register on falling edges of the serial
shift clock, S CLK. The LSB should be shifted in first and
the MSB last as shown in Timing Diagram 1. The data that
has been shifted into the shift register is loaded into a 16-
bit data latch on the falling edge of S ENABLE. To insure
that true data is loaded into the data latch from the shift
register, the S ENABLE falling edge should occur before
the S CLK transitions high to low. S ENABLE should be
high while shifting data into the shift register. Note that
all data is entered and latched on edges, not levels, of S
CLK and S ENABLE.
POWER SUPPLIES
The analog circuitry in the device is powered from 5V
(AV ) and is referenced to AGND. The digital circuits in
CC
Upon power up, the data in the latch is indeterminate. It
is therefore recommended to initialize the frequency data
as part of a power up routine.
the device can also powered from the same 5V supply
(DV to DGND). It is recommended that AGND and
CC
DGND be connected together close to the device and
have a good connection back to the power source.
It is recommended that the power supplies to the device
should be bypassed by placing decoupling capacitors
from AV to AGND and DV to DGND as physically
CC
CC
close to the device as possible.
SNYC
500ns
1 µs
OUT
Figure 2. SYNC Pin Timing.
7
MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
