ML2037
PIN CONFIGURATION
ML2037
16-Pin PDIP (P16)
16-Pin Wide SOIC (S16W)
D GND
SYNC
1
2
3
4
5
6
7
8
16 DV
15 G1
14 G0
CC
CLK OUT
S CLK
13 CLK IN
D GND
S DATA IN
S ENABLE
SHDN
12 AV
11 AV
CC
CC
10 OUT
A GND
9
TOP VIEW
PIN DESCRIPTION
PIN NAME
FUNCTION
PIN NAME
FUNCTION
1, 5 D GND
Ground connection for the digital
sections of the IC.
9
A GND
Ground reference for analog sections
of the IC and reference for OUT.
2
SYNC
Synchronization input. Holding this
pin low stops the sine wave output,
and resets the phase to zero.
10
OUT
Sine wave output. The amplitude of
the sine wave will vary around a 2.5V
DC level.
3
4
CLK OUT Output of the internal high frequency
clock generator. f = ½f
11,12 AV
Power supply for the analog sections of
the IC.
CC
.
CLK IN
CLK OUT
S CLK
Serial data clock input. Serial data is
clocked into the shift register on
falling edges of S CLK.
13
CLK IN
Input of the internal high frequency
clock generator. This pin is either
driven from an external clock input or
connected to a crystal for use with the
internal oscillator.
6
7
S DATA IN Serial data input for programming the
output frequency.
14
15
16
G0
G1
Output gain control. Works with G1 to
set the output amplitude to one of four
different full scale ranges.
S ENABLE Serial interface enable control. A
logic high on this pin allows data to be
entered into the latch.
Output gain control. Works with G0 to
set the output amplitude to one of four
different full scale ranges.
8
SHDN
A logic high on this pin causes the
output of the generator to shut off and
places the IC in a low power standby
mode.
DV
Power supply for the digital sections of
the IC.
CC
2
MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
