ML2008, ML2009
D8
D7 D6 D5 D4 D3 D2 D1 BIT
ATTEN/GAIN C3 C2 C1 C0 F3 F2 F1 REG 0
A0 = 0
A0 = 1
D8
D7 D6 D5 D4 D3 D2 D1 D0
BIT
ATTEN/GAIN C3 C2 C1 C0 F3 F2 F1 F0
REG 0
P
DN
F0 REG 1
Figure 11. ML2009 Register Structure
Figure 10. ML2008 Register Structure
ML2008
ML2009
V
IN
V
OUT
V
V
OUT
IN
CS
D0
WR
D1-D8
CS
WR
A0 D1-D8
+5V
µP
µP
8
8
Figure 13. Typical 8-Bit µP Interface, Single Write
Figure 12. Typical 8-Bit µP Interface, Double Write
ML2009
ML2009
ML2233
12-BIT
+ SIGN
A/D
V
V
OUT
V
IN
IN
WR
D0-D8
CS
CS
WR
D0-D8
µP
OR
DSP
µP
9
Figure 14. Typical 16-Bit µP Interface
Figure 15. AGC for DSP or Modem Front End
8