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ML2008IQ 参数 Datasheet PDF下载

ML2008IQ图片预览
型号: ML2008IQ
PDF下载: 下载PDF文件 查看货源
内容描述: レP兼容的对数增益/衰减器 [レP Compatible Logarithmic Gain/Attenuator]
分类和应用: 电信集成电路衰减器
文件页数/大小: 11 页 / 158 K
品牌: MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
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ML2008, ML2009  
PIN CONFIGURATION  
ML2008  
18-Pin DIP (P18)  
ML2009*  
18-Pin DIP (P18)  
D7  
D6  
1
2
3
4
5
6
7
8
9
18  
17  
16  
15  
14  
13  
12  
11  
10  
D8  
D7  
D6  
1
2
3
4
5
6
7
8
9
18  
17  
16  
15  
14  
13  
12  
11  
10  
D8  
V
V
V
V
V
V
CC  
CC  
D5  
OUT  
SS  
D5  
OUT  
SS  
D4  
D4  
AGND  
AGND  
WR  
D3  
WR  
D3  
V
V
IN  
IN  
D2  
NC  
CS  
A0  
D2  
NC  
CS  
D1  
D1  
GND  
GND  
D0  
TOP VIEW  
TOP VIEW  
20-Pin PLCC (Q20)  
20-Pin PLCC (Q20)  
3
2
1
20 19  
3
2
1
20 19  
D4  
D4  
NC  
WR  
D3  
D2  
4
5
6
7
8
4
5
6
7
8
18  
17  
16  
15  
14  
18  
17  
16  
15  
14  
V
V
V
V
OUT  
SS  
OUT  
SS  
NC  
WR  
D3  
AGND  
NC  
AGND  
NC  
D2  
NC  
NC  
9
10 11 12 13  
9
10 11 12 13  
TOP VIEW  
TOP VIEW  
PIN DESCRIPTION  
NAME  
FUNCTION  
NAME  
D3  
FUNCTION  
V
V
Negative supply. 5Volts ±10%  
Positive supply. 5Volts ±10%  
Data bit, F3  
SS  
D2  
Data bit, P , F2 ML2008; F2 ML2009  
CC  
DN  
GND  
Digital ground. 0Volts. All digital  
D1  
Data bit, F0, F1 ML2008; F1 ML2009  
Data bit, F0 ML2009 only  
inputs are referenced to this ground.  
D0  
AGND  
Analog ground. 0Volts. Analog input  
and output are referenced to this  
ground.  
WR  
Write enable. This input latches the  
data bits into the registers on rising  
edges of WR.  
V
V
Analog input  
Analog output  
Data bit, ATTEN/GAIN  
Data bit, C3  
IN  
CS  
Chip select. This input selects the  
device by only allowing the WR signal  
to latch in data when CS is low.  
OUT  
D8  
D7  
D6  
D5  
D4  
A0  
Address select. This input determines  
which data word is being written into  
the registers.  
(ML2008 only)  
Data bit, C2  
Data bit, C1  
Data bit, C0  
2