ML2008, ML2009
D8
A0 = 0
A0 = 1
ATTEN/GAIN
D7
C3
D6
C2
D5
C1
D4
C0
D3
F3
D2
F2
P
DN
D1
F1
F0
BIT
REG 0
REG 1
D8
ATTEN/GAIN
D7
C3
D6
C2
D5
C1
D4
C0
D3
F3
D2
F2
D1 D0
F1
F0
BIT
REG 0
Figure 10. ML2008 Register Structure
Figure 11. ML2009 Register Structure
ML2008
V
IN
V
OUT
V
IN
ML2009
V
OUT
CS WR
A0
D1-D8
CS WR
D1-D8 D0
+5V
µP
8
µP
8
Figure 12. Typical 8-Bit
µP
Interface, Double Write
Figure 13. Typical 8-Bit
µP
Interface, Single Write
ML2009
V
IN
ML2009
V
OUT
D0-D8 WR CS
ML2233
12-BIT
V
IN
+ SIGN
A/D
µP
OR
DSP
CS WR
D0-D8
µP
9
Figure 14. Typical 16-Bit
µP
Interface
Figure 15. AGC for DSP or Modem Front End
8