MIC2584/2585
Micrel
The sequenced output feature is enabled for the MIC2585 by
placing a capacitor from CDLY to ground. The –1 option
C
t
OCSLOW
FILTER
220pF
680pF
110µs
allows for V
to follow V
and the –2 option allows for
OUT2
OUT1
340µs
500µs
1.6ms
5ms
V
to follow V
during start-up (See "Timing Dia-
OUT1
OUT2
grams, Figure 5"). The sequenced output delay time is
determined using the following equation:
1000pF
3300pF
0.01µF
0.047µF
0.1µF
V
DELAY
t
C
×
0.2 × C
(µF)
(9)
DLY
DLY
DLY
I
DELAY
23.5ms
50ms
where V
, the CDLY pin threshold, is typically 1.235V,
DELAY
I
, the CDLY pin charge current, is typically 6µA, and
DELAY
0.33µF
165ms
C
is the capacitor connected to CDLY. Tables 2, 3, and 4
DLY
provide a quick reference for several timer calculations using
select standard value capacitors.
Table 3. Selected Overcurrent Timer Delays
C
t
DLY
Undervoltage Lockout
DLY
4700pF
0.01µF
0.047µF
0.1µF
950µs
2ms
Internal circuitry keeps both GATE output charge pumps off
untilVCC1andVCC2exceed2.165Vand0.8V, respectively.
C
t
t
POR
9.5ms
20ms
66ms
165ms
200ms
440ms
POR
START
0.01µF
0.033µF
0.05µF
0.1µF
1.2ms
4ms
5ms
16.5ms
25ms
0.33µF
0.82µF
1µF
6ms
12ms
40ms
56ms
120ms
50ms
0.33µF
0.47µF
1µF
165ms
235ms
500ms
2.2µF
Table 4. Selected Sequenced Output Delays
Table 2. Selected Power-On Reset and
Start-Up Delays
March 2005
17
MIC2584/2585
MICREL [ MICREL SEMICONDUCTOR ]
