KSZ8795CLX
The KSZ8795CLX will not forward the following packets:
• Error packets. These include framing errors, frame check sequence (FCS) errors, alignment errors, and illegal
size packet errors.
• IEEE802.3x PAUSE frames. KSZ8795CLX intercepts these packets and performs full duplex flow control accord-
ingly.
• "Local" packets. Based on destination address (DA) lookup, if the destination port from the lookup table matches
the port from which the packet originated, the packet is defined as "local."
FIGURE 3-4:
DESTINATION ADDRESS LOOKUP AND RESOLUTION FLOW CHART
START
PTF 1
- CHECK RECEIVING PORT’S RECEIVE ENABLE BIT
- CHECK DESTINATION PORT’S TRANSMIT ENABLE BIT
- CHECK WHETHER PACKETS ARE SPECIAL (BPDU)
- SEARCH VLAN TABLE
- INGRESS VLAN FILTERING
- DISCARD NPVID CHECK
SPANNING
TREE
PROCESS
NO
VLAN ID
VALID?
PTF 1 = NULL
- APPLIED TO MAC (#1 TO #4)
- MAC #5 IS RESERVED FOR µC
- IGMP WILL BE FORWARDED TO PORT 5
YES
IGMP
PROCESS
- SEARCH BASED ON
DA OR DA + FID
FOUND
GET PTF 1
FROM STATIC
ARRAY
SEARCH
STATIC
ARRAY
- RX MIRROR
- TX MIRROR
- RX OR TX MIRROR
- RX AND TX MIRROR
PORT
MIRROR
PROCESS
NOT FOUND
- SEARCH BASED ON
DA + FID
FOUND
SEARCH
ADDRESS
LOOK-UP
TABLE
GET PTF 1
FROM ADDRESS
TABLE
PORT VLAN
MEMBERSHIP
CHECK
NOT FOUND
PORT
AUTHENTICATION
AND ACL
GET PTF 1 FROM
VLAN TABLE
PTF 2
PTF 2
3.3.6
SWITCHING ENGINE
The KSZ8795CLX features a high-performance switching engine to move data to and from the MAC’s packet buffers.
It operates in store and forward mode, while the efficient switching mechanism reduces overall latency. The KSZ8795-
CLX has a 64 kB internal frame buffer. This resource is shared between all five ports. There are a total of 512 buffers
available. Each buffer is sized at 128 bytes.
3.4
Power and Power Management
The KSZ8795CLX device requires 3.3V analog power. An external 1.2V LDO provides the necessary 1.2V to power the
analog and digital logic cores. The various I/Os can be operated at 1.8V, 2.5V, and 3.3V. Table 3-2 illustrates the various
voltage options and requirements of the device.
TABLE 3-2:
KSZ8795CLX VOLTAGE OPTIONS AND REQUIREMENTS
Power Signal
Name
Device Pin
Requirement
VDDAT
2, 12, 76
3.3V or 2.5V input power to the analog blocks of transceiver in the
device.
VDDIO
34, 48, 70
Choice of 1.8V or 2.5V or 3.3V for the I/O circuits. These input power
pins power the I/O circuitry of the device.
DS00002112A-page 20
2016 Microchip Technology Inc.
MICREL [ MICREL SEMICONDUCTOR ]
