KS8721B/BT
Micrel
TXC
tHD2
tSU2
TXEN
tHD1
tSU1
TXD[3:0],
TXER
Data
In
tCRS2
tCRS1
tLAT
CRS
Symbol
Out
TX+/TX-
Figure 5. 100BaseT MII Transmit Timing
Symbol
tSU1
Parameter
Min
10
10
0
Typ
Max
Units
ns
TXD [3:0] Set-Up to TXC High
TXEN Set-Up to TXC High
tSU2
ns
tHD1
TXD [3:0] Hold After TXC High
TXER Hold After TXC High
ns
tHD2
0
ns
tHD3
TXEN Hold After TXC High
0
ns
tCRS1
tCRS2
tLAT
TXEN High to CRS Asserted Latency
TXEN Low to CRS De-Asserted Latency
TXEN High to TX+/TX– Output (TX Latency)
4
4
7
BT
BT
BT
Table 3. 100BaseT MII Transmit Timing Parameters
August 2003
25
KS8721B/BT