KS8721B/BT
Micrel
Timing Diagrams
TXC
tHD2
tSU2
TXEN
tHD1
TXD[3:0]
CRS
tSU1
tCRS1
tCRS2
Valid
Data
TXP/TXM
tLAT
SQE Timing
TXC
TXEN
COL
tSQE
tSQEP
Figure 4. 10BaseT MII Transmit Timing
Symbol
tSU1
Parameter
Min
10
10
0
Typ
Max
Units
ns
TXD [3:0] Set-Up to TXC High
TXEN Set-Up to TXC High
TXD [3:0] Hold After TXC High
TXEN Hold After TXC High
tSU2
ns
tHD1
ns
tHD2
0
ns
tCRS1
tCRS2
tLAT
TXEN High to CRS Asserted Latency
TXEN Low to CRS De-Asserted Latency
TXEN High to TXP/TXM Output (TX Latency)
COL (SQE) Delay Aftter TXEN Ae-Asserted
COL (SQE) Pulse Duration
4
8
BT
BT
BT
µs
4
tSQE
2.5
1.0
tSQEP
µs
Table 2. 10BaseT MII Transmit Timing Parameters
KS8721B/BT
24
August 2003
MICREL [ MICREL SEMICONDUCTOR ]
