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KSZ8721BLITR 参数 Datasheet PDF下载

KSZ8721BLITR图片预览
型号: KSZ8721BLITR
PDF下载: 下载PDF文件 查看货源
内容描述: [DATACOM, ETHERNET TRANSCEIVER, PQFP48, LEAD FREE, LQFP-48]
分类和应用: 局域网(LAN)标准
文件页数/大小: 32 页 / 201 K
品牌: MICREL [ MICREL SEMICONDUCTOR ]
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KS8721B/BT  
Micrel  
Transmit Data [1:0] (TXD[1:0])  
Transmit Data TXD[1:0] shall transition synchronously with respect to REF_CLK. When TX_EN is asserted, TXD[1:0] are  
accepted for transmission by the PHY. TXD[1:0] shall be 00to indicate idle when TX_EN is de-asserted. Values of TXD[1:0]  
other than 00when TX_EN is de-asserted are reserved for out-of-band signalling (to be defined). Values other than 00on  
TXD[1:0] while TX_EN is deasserted shall be ignored by the PHY.  
Collision Detection  
Since the definition of CRS_DV and TX_EN both contain an accurate indication of the start of frame, the MAC can reliably  
regenerate the COL signal of the MII by ANDing TX_EN and CRS_DV.  
During the IPG time following the successful transmission of a frame, the COL signal is asserted by some transceivers as a  
self-test. The Signal Quality Error (SQE) function will not be supported by the reduced MII due to the lack of the COL signal.  
Historically, SQE was present to indicate that a transceiver located physically remote from the MAC was functioning. Since  
the reduced MII only supports chip-to-chip connections on a PCB, SQE functionality is not required.  
RX_ER  
The PHY shall provide RX_ER as an output according to the rules specified in IEEE 802.3u [2] (see Clause 24, Figure 24-11  
- Receive State Diagram). RX_ER shall be asserted for one or more REF_CLK periods to indicate that an error (e.g. a coding  
error or any error that a PHY is capable of detecting, and that may otherwise be undetectable by the MAC sublayer) was  
detectedsomewhereintheframepresentlybeingtransferredfromthePHY.RX_ERshalltransitionsynchronouslywithrespect  
to REF_CLK. While CRS_DV is de-asserted, RX_ER shall have no effect on the MAC.  
RMII AC Characteristics  
Symbol  
Parameter  
Min  
Typ  
Max  
Units  
MHz  
%
REF_CLK Frequency  
REF_CLK Duty Cycle  
50  
35  
4
65  
tSU  
tH  
TXD[1:0]. TX_EN, RXD[1:0], CRS_DV,  
RX_ER Data Set-Up to REF_CLK Rising  
ns  
TXD[1:0]. TX_EN, RXD[1:0], CRS_DV,  
RXER Data Hold from REF_CLK  
Rising Edge  
2
ns  
KS8721B/BT  
14  
August 2003