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KSZ8721BLITR 参数 Datasheet PDF下载

KSZ8721BLITR图片预览
型号: KSZ8721BLITR
PDF下载: 下载PDF文件 查看货源
内容描述: [DATACOM, ETHERNET TRANSCEIVER, PQFP48, LEAD FREE, LQFP-48]
分类和应用: 局域网(LAN)标准
文件页数/大小: 32 页 / 201 K
品牌: MICREL [ MICREL SEMICONDUCTOR ]
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KS8721B/BT  
Micrel  
Collision: Whenever the line state is half-duplex and the transmitter and receiver are active at the same time, the KS8721B/  
BT asserts its collision signal, which is asynchronous to any clock.  
RMII (Reduced MII) Data Interface  
RMII interface specifies a low pin count (Reduced) Media Independent Interface (RMII) intended for use between Ethernet  
PHYs and Switch or Repeater ASICs. It is fully compliant with IEEE 802.3u [2].  
This interface has the following characteristics:  
It is capable of supporting 10Mbps and 100Mbps data rates.  
A single clock reference is sourced from the MAC to PHY (or from an external source).  
It provides independent 2-bit wide (di-bit) transmit and receive data paths.  
It uses TTL signal levels, compatible with common digital CMOS ASIC processes.  
RMII Signal Definition  
Direction  
Direction  
Signal Name  
(w/ respect to the PHY)  
(w/ respect to the MAC)  
Use  
REF_CLK  
Input  
Input or Output  
Synchronous clock reference for receive, transmit and  
control interface  
CRS_DV  
RXD[1:0]  
TX_EN  
Output  
Output  
Input  
Input  
Carrier Sense/Receive Data Valid  
Receive Data  
Input  
Output  
Transit Enable  
TXD[1:0]  
RX_ER  
Input  
Output  
Transit Data  
Output  
Input (Not Required)  
Receive Error  
Note 1. Unused MII signals, TXD[3:2], TXER need to tie to GND when RMII is using.  
Reference Clock (REF_CLK)  
REF_CLK is a continuous 50MHz clock that provides the timing reference for CRS_DV, RXD[1:0], TX_EN, TXD[1:0], and  
RX_E. REF_CLK is sourced by the MAC or an external source. Switch implementations may choose to provide REF_CLK as  
an input or an output depending on whether they provide a REF_CLK output or rely on an external clock distribution device.  
Each PHY device shall have an input corresponding to this clock but may use a single clock input for multiple PHYs  
implemented on a single IC.  
Carrier Sense/Receive Data Valid (CRS_DV)  
CRS_DV is asserted asynchronously on detection of carrier due to the criteria relevant to the operating mode. That is, in  
10BASE-Tmode,whensquelchispassedorin100BASE-Xmodewhen2non-contiguouszeroesin10bitsaredetectedcarrier  
is said to be detected.  
Loss of carrier shall result in the de-assertion of CRS_DV synchronous to REF_CLK. So long as carrier criteria are being met,  
CRS_DV shall remain asserted continuously from the first recovered di-bit of the frame through the final recovered di-bit and  
shall be negated prior to the first REF_CLK that follows the final di-bit.  
ThedataonRXD[1:0]isconsideredvalidonceCRS_DVisasserted.However,sincetheassertionofCRS_DVisasynchronous  
relative to REF_CLK, the data on RXD[1:0] shall be 00until proper receive signal decoding takes place (see definition of  
RXD[1:0] behavior).  
Receive Data [1:0] (RXD[1:0])  
RXD[1:0] shall transition synchronously to REF_CLK. For each clock period in which CRS_DV is asserted, RXD[1:0] transfers  
two bits of recovered data from the PHY. In some cases (e.g. before data recovery or during error conditions) a pre-determined  
value for RXD[1:0] is transferred instead of recovered data. RXD[1:0] shall be 00to indicate idle when CRS_DV is de-  
asserted. Values of RXD[1:0] other than 00when CRS_DV is de-asserted are reserved for out-of-band signalling (to be  
defined). Values other than 00on RXD[1:0] while CRS_DV is de-asserted shall be ignored by the MAC/repeater. Upon  
assertion of CRS_DV, the PHY shall ensure that RXD[1:0]=00 until proper receive decoding takes place.  
Transmit Enable (TX_EN)  
Transmit Enable TX_EN indicates that the MAC is presenting di-bits on TXD[1:0] on the RMII for trans-mission. TX_EN shall  
be asserted synchronously with the first nibble of the preamble and shall remain asserted while all di-bits to be transmitted are  
presented to the RMII. TX_EN shall be negated prior to the first REF_CLK following the final di-bit of a frame. TX_EN shall  
transition synchronously with respect to REF_CLK.  
August 2003  
13  
KS8721B/BT