Micrel, Inc.
KSZ9021RL/RN
Pin Number
Pin Name
RXD3 /
Type(1)
Pin Function
RGMII Mode:
Config Mode:
36
I/O
RGMII RD3 (Receive Data 3) Output /
MODE3
The pull-up/pull-down value is latched as MODE3 during
power-up / reset. See “Strapping Options” section for details.
37
38
DVDDH
RXD2 /
MODE2
P
3.3V / 2.5V digital VDD
I/O
RGMII Mode:
Config Mode:
RGMII RD2 (Receive Data 2) Output /
The pull-up/pull-down value is latched as MODE2 during
power-up / reset. See “Strapping Options” section for details.
39
40
41
VSS
Gnd
P
Digital ground
1.2V digital VDD
RGMII Mode:
Config Mode:
DVDDL
RXD1 /
MODE1
I/O
RGMII RD1 (Receive Data 1) Output /
The pull-up/pull-down value is latched as MODE1 during
power-up / reset. See “Strapping Options” section for details.
42
43
RXD0 /
I/O
I/O
RGMII Mode:
Config Mode:
RGMII RD0 (Receive Data 0) Output /
MODE0
The pull-up/pull-down value is latched as MODE0 during
power-up / reset. See “Strapping Options” section for details.
RX_DV /
RGMII Mode:
Config Mode:
RGMII RX_CTL (Receive Control) Output /
CLK125_EN
Latched as CLK125_NDO Output Enable during power-up /
reset. See “Strapping Options” section for details.
44
45
46
DVDDH
RX_ER
P
O
3.3V / 2.5V digital VDD
RGMII Mode:
RGMII Mode:
Config Mode:
This pin is not used and should be left as a no connect.
RX_CLK /
PHYAD2
I/O
RGMII RXC (Receive Reference Clock) Output /
The pull-up/pull-down value is latched as PHYAD[2] during
power-up / reset. See “Strapping Options” section for details.
47
48
CRS
MDC
O
RGMII Mode:
This pin is not used and should be left as a no connect.
Ipu
Management Data Clock Input
This pin is the input reference clock for MDIO (pin 49).
Management Data Input / Output
49
MDIO
Ipu/O
This pin is synchronous to MDC (pin 48) and requires an external pull-up resistor
to 3.3V digital VDD in a range from 1.0KΩ to 4.7KΩ.
50
51
COL
O
O
RGMII Mode:
This pin is not used and should be left as a no connect.
INT_N
Interrupt Output
This pin provides a programmable interrupt output and requires an external pull-up
resistor to 3.3V digital VDD in a range from 1.0KΩ to 4.7KΩ when active low.
Register 1Bh is the Interrupt Control/Status Register for programming the interrupt
conditions and reading the interrupt status. Register 1Fh bit 14 sets the interrupt
output to active low (default) or active high.
52
53
54
55
DVDDL
VSS
P
Gnd
P
1.2V digital VDD
Digital ground
DVDDL
1.2V digital VDD
CLK125_NDO /
I/O
125MHz Clock Output
This pin provides a 125MHz reference clock output option for use by the MAC. /
LED_MODE
Config Mode:
The pull-up/pull-down value is latched as LED_MODE during
power-up / reset. See “Strapping Options” section for details.
M9999-101309-1.1
October 2009
12
MICREL [ MICREL SEMICONDUCTOR ]
