WME128K8-XXX
WRITE
WRITE CYCLE TIMING
Write operations are initiated when both CS# and WE# are low
and OE# is high. The EEPROM devices support both a CS# and
WE# controlled write cycle. The address is latched by the falling
edge of either CS# or WE#, whichever occurs last.
Figures 4 and 5 show the write cycle timing relationships. A write
cycle begins with address application, write enable and chip select.
Chip select is accomplished by placing the CS# line low. Write
enable consists of setting the WE# line low. The write cycle begins
when the last of either CS# or WE# goes low.
The data is latched internally by the rising edge of either CS#
or WE#, whichever occurs first. A byte write operation will
automatically continue to completion.
The WE# line transition from high to low also initiates an internal
150μsec delay timer to permit page mode operation. Each
subsequent WE# transition from high to low that occurs before the
completion of the 150μsec time out will restart the timer from zero.
The operation of the timer is the same as a retriggerable one-shot.
AC WRITE CHARACTERISTICS
VCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C
128Kx8
Parameter
Symbol
Unit
Min
Max
Write Cycle Time, TYP = 6ms
Address Set-up Time
tWC
10
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAS
tWP
tCS
10
100
0
Write Pulse Width (WE# or CS#)
Chip Select Set-up Time
Address Hold Time
tAH
100
10
0
Data Hold Time
tDH
Chip Select Hold Time
Data Set-up Time
tCH
tDS
50
0
Output Enable Set-up Time
Output Enable Hold Time
Write Pulse Width High
tOES
tOEH
tWPH
0
50
4
4311.11E-0718-ss-WME128K8-XXX
Mercury Corp. - Memory and Storage Solutions • (602) 437-1520 • www.mrcy.com
MERCURY [ MERCURY UNITED ELECTRONICS INC ]
