WEDPN16M64V-XB2X
PRELIMINARY
When a READ or WRITE command is issued, a block of columns
equal to the burst length is effectively selected. All accesses for
that burst take place within this block, meaning that the burst will
wrap within the block if a boundary is reached. The block is uniquely
selected byA1-8 when the burst length is set to two; byA2-8 when
the burst length is set to four; and by A3-8 when the burst length
is set to eight. The remaining (least significant) address bit(s) is
(are) used to select the starting location within the block. Full-page
bursts wrap within the page if the boundary is reached.
piece of output data. The latency can be set to two or three clocks.
If a READ command is registered at clock edge n, and the latency
is m clocks, the data will be available by clock edge n+m. The I/
Os will start driving as a result of the clock edge one cycle earlier
(n + m - 1), and provided that the relevant access times are met,
the data will be valid by clock edge n + m. For example, assuming
that the clock cycle time is such that all relevant access times are
met, if a READ command is registered at T0 and the latency is
programmed to two clocks, the I/Os will start driving after T1 and the
data will be valid by T2. Table 2 indicates the operating frequencies
at which each CAS latency setting can be used.
BURST TYPE
Accesses within a given burst may be programmed to be either
sequential or interleaved; this is referred to as the burst type and
is selected via bit M3.
Reserved states should not be used as unknown operation or
incompatibility with future versions may result.
The ordering of accesses within a burst is determined by the burst
length, the burst type and the starting column address, as shown
in Table 1.
OPERATING MODE
The normal operating mode is selected by setting M7and M8 to
zero; the other combinations of values for M7 and M8 are reserved
for future use and/or test modes. The programmed burst length
applies to both READ and WRITE bursts.
TABLE 1 – BURST DEFINITION
Order of Accesses Within a Burst
Burst
Length
Starting Column
Address
Test modes and reserved states should not be used because
unknown operation or incompatibility with future versions may
result.
Type = Sequential
Type = Interleaved
A0
2
4
0
1
0-1
1-0
0-1
1-0
TABLE 2 - CAS LATENCY
A1
A0
0
ALLOWABLE OPERATING
FREQUENCY (MHz)
0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0
1
SPEED
-100
CAS LATENCY = 2
CAS LATENCY = 3
1
0
-75
-100
-125
1
1
-125
-100
A2
0
A1
A0
0
0
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
-133
-100
-133
0
0
1
0
1
0
WRITE BURST MODE
8
0
1
1
1
0
0
When M9 = 0, the burst length programmed via M0-M2 applies
to both READ and WRITE bursts; when M9 = 1, the programmed
burst length applies to READ bursts, but write accesses are single-
location (nonburst) accesses.
1
0
1
1
1
0
1
1
1
n = A0-9/8/7
Cn, Cn + 1, Cn + 2
Cn + 3, Cn + 4...
…Cn - 1, Cn…
Full
Page (y)
Not Supported
COMMANDS
(location 0-y)
NOTES:
1. For full-page accesses: y = 512.
2. For a burst length of two, A1-8 select the block-of-two burst; A0 selects the starting column
within the block.
3. For a burst length of four, A2-8 select the block-of-four burst; A0-1 select the starting column
within the block.
The Truth Table provides a quick reference of available commands.
This is followed by a written description of each command. Three
additional Truth Tables appear following the Operation section;
these tables provide current state/next state information.
4. For a burst length of eight, A3-8 select the block-of-eight burst; A0-2 select the starting column
within the block.
COMMAND INHIBIT
5. For a full-page burst, the full row is selected and A0-8 select the starting column.
6. Whenever a boundary of the block is reached within a given sequence above, the following
access wraps within the block.
7. For a burst length of one, A0-8 select the unique column to be accessed, and Mode Register bit
M3 is ignored.
The COMMAND INHIBIT function prevents new commands from
being executed by the SDRAM, regardless of whether the CLK
signal is enabled. The SDRAM is effectively deselected. Operations
already in progress are not affected.
CAS LATENCY
NO OPERATION (NOP)
The CAS latency is the delay, in clock cycles, between the
registration of a READ command and the availability of the first
The NO OPERATION (NOP) command is used to perform a NOP
to an SDRAM which is selected (CS# is LOW). This prevents
Microsemi Corporation reserves the right to change products or specifications without notice.
July 2011 © 2011 Microsemi Corporation. All rights reserved.
Rev. 1
5
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