W78M32VP-XBX
or unprotected. That is, sector protection or unprotection for
these sectors depends on whether they were last protected or
unprotected.
The RESET# input provides a hardware method of resetting the
device to reading array data. When RESET# is driven low for
at least a period of tRP, the device immediately terminates any
operation in progress, tristates all outputs, and ignores all read/
write commands for the duration of the RESET# pulse. The device
also resets the internal state machine to reading array data. The
operation that was interrupted should be reinitiated once the
device is ready to accept another command sequence to ensure
data integrity.
The WP#/ACC pin must be held stable during a command sequence
execution. WP# has an internal pull-up; when unconnected, WP#
is set at VIH.
NOTE
If WP#/ACC is at VIL when the device is in the standby mode, the
maximum input load current is increased.
When RESET# is held at VSS ± 0.3 V, the device draws ICC reset
current (ICC5). If RESET# is held at VIL but not within VSS ± 0.3 V,
the standby current is greater.
LOW VCC WRITE INHIBIT
When VCC is less than VLKO, the device does not accept any write
cycles. This protects data during VCC power-up and power-down.
The command register and all internal program/erase circuits are
disabled, and the device resets to reading array data. Subsequent
writes are ignored until VCC is greater than VLKO. The system
must provide the proper signals to the control inputs to prevent
RESET# may be tied to the system reset circuitry and thus, a
system reset would also reset the Flash memory, enabling the
system to read the boot-up firmware from the Flash memory.
OUTPUT DISABLE (OE#)
When the OE# input is at VIH, output from the device is disabled.
The outputs are placed in the high impedance state. (With the
exception of RY/BY#.)
unintentional writes when VCC is greater than VLKO
.
WRITE PULSE “GLITCH PROTECTION”
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do
not initiate a write cycle.
SECURED SILICON SECTOR FLASH
MEMORY REGION
Secured Silicon Sector Flash Memory Region The Secured Silicon
Sector provides an extra Flash memory region that enables
permanent part identification through an Electronic Serial Number
(ESN). The Secured Silicon Sector is 128 words in length and all
Secured Silicon reads outside of the 128-word address range
returns invalid data. The Secured Silicon Sector Indicator Bit, DQ7,
(at Autoselect address 03h) is used to indicate whether or not the
Secured Silicon Sector is locked when shipped from the factory.
POWER-UP WRITE INHIBIT
If WE# = CE# = RESET# = VIL and OE# = VIH during power up,
the device does not accept commands on the rising edge of WE#.
The internal state machine is automatically reset to the read mode
on power-up.
POWER CONSERVATION MODES
STANDBY MODE
Please note the following general conditions:
On power-up, or following a hardware reset, the device
When the system is not reading or writing to the device, it can
place the device in the standby mode. In this mode, current
consumption is greatly reduced, and the outputs are placed in the
high impedance state, independent of the OE# input. The device
enters the CMOS standby mode when the CE# and RESET# inputs
are both held at VCC ± 0.3 V. The device requires standard access
time (tCE) for read access, before it is ready to read data. If the
device is deselected during erasure or programming, the device
draws active current until the operation is completed. ICC4 in “DC
Characteristics” represents the standby current specification
reverts to sending commands to the normal address space.
Reads outside of sector SA0 return memory array data.
Sector SA0 is remapped from memory array to Secured
Silicon Sector array.
Once the Secured Silicon Sector Entry Command is issued,
the Secured Silicon Sector Exit command must be issued to
exit Secured Silicon Sector Mode.
The Secured Silicon Sector is not accessible when the
device is executing an Embedded Program or Embedded
Erase algorithm.
AUTOMATIC SLEEP MODE
The ACC function and unlock bypass modes are not
The automatic sleep mode minimizes Flash device energy
consumption. The device automatically enables this mode
when addresses remain stable for tACC + 30 ns. The automatic
sleep mode is independent of the CE#, WE#, and OE# control
signals. Standard address access timings provide new data when
addresses are changed. While in sleep mode, output data is latched
and always available to the system. ICC6 represents the automatic
sleep mode current specification.
available when the Secured Silicon Sector is enabled.
FACTORY LOCKED SECURED SILICON
SECTOR
The Factory Locked Secured Silicon Sector is always protected
when shipped from the factory and has the Secured Silicon Sector
Indicator Bit (DQ7) permanently set to a “1”. This prevents cloning
of a factory locked part and ensures the security of the ESN and
customer code once the product is shipped to the field.
HARDWARE RESET# INPUT OPERATION
Microsemi Corporation reserves the right to change products or specifications without notice.
August 2011 © 2011 Microsemi Corporation. All rights reserved.
Rev. 15
11
Microsemi Corporation • (602) 437-1520 • www.microsemi.com
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