W3H128M72E-XSBX / W3H128M72E-XNBX
CAS LATENCY (CL)
The CAS latency (CL) is defined by bits M4–M6, as shown in Figure
5. CL is the delay, in clock cycles, between the registration of a
READ command and the availability of the first bit of output data.
The CL can be set to 4, 5, 6 or 7 clocks, depending on the speed
grade option being used.
DDR2 SDRAM also supports a feature called posted CAS additive
latency (AL). This feature allows the READ command to be issued
prior to tRCD (MIN) by delaying the internal command to the DDR2
SDRAM by AL clocks.
An example of CL = 4 is shown in Figure 6; assume AL = 0. If a
READ command is registered at clock edge n, and the CL is m
clocks, the data will be available nominally coincident with clock
edge n+m (this assumes AL = 0).
DDR2 SDRAM does not support any half-clock latencies. Reserved
states should not be used as unknown operation or incompatibility
with future versions may result.
FIGURE 6 – CAS LATENCY (CL)
T0
T1
T2
T3
T4
T5
T6
CK#
CK
READ
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
DQS, DQS#
D
OUT
D
OUT
D
OUT
DOUT
n + 3
DQ
n
n + 1
n + 2
CL = 4 (AL = 0)
Burst length = 4
Posted CAS# additive latency (AL) = 0
Shown with nominal tAC, tDQSCK and tDQSQ
TRANSITIONING DATA
DON’T CARE
9
4163.12E-0716-ss-W3H128M72E-XSBX / XNBX
Mercury Corp. - Memory and Storage Solutions • (602) 437-1520 • www.mrcy.com
MERCURY [ MERCURY UNITED ELECTRONICS INC ]
