W3H128M72E-XSBX / W3H128M72E-XNBX
FIGURE 5 – MODE REGISTER (MR) DEFINITION
MODE REGISTER (MR)
The mode register is used to define the specific mode of operation
of the DDR2 SDRAM. This definition includes the selection of a
burst length, burst type, CAS latency, operating mode, DLLRESET,
write recovery, and power-down mode, as shown in Figure 5.
Contents of the mode register can be altered by re-executing the
LOAD MODE (LM) command. If the user chooses to modify only
a subset of the MR variables, all variables must be programmed
when the command is issued.
BA2 BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
16 15 14 13 12 11 10
9
7
6
5
4
3
2
1
0
8
Mode Register (Mx)
0
MR
0
PD
WR
DLL TM CAS# Latency BT Burst Length
Mode
Normal
Test
M7
0
M2 M1 M0
Burst Length
Reserved
Reserved
4
The mode register is programmed via the LM command will
retain the stored information until it is programmed again or the
device loses power (except for bit M8, which is self-clearing).
Reprogramming the mode register will not alter the contents of
the memory array, provided it is performed correctly.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
PD mode
Fast Exit
(Normal)
Slow Exit
M12
0
DLL Reset
No
M8
0
8
1
Reserved
Reserved
Reserved
Reserved
1
Yes
(Low Power)
The LM command can only be issued (or reissued) when all
banks are in the precharged state (idle state) and no bursts are in
progress. The controller must wait the specified time tMRD before
initiating any subsequent operations such as anACTIVE command.
Violating either of these requirements will result in unspecified
operation.
WRITE RECOVERY
M11 M10 M9
Reserved
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
8
Burst Type
Sequential
Interleaved
M3
0
1
BURST LENGTH
CAS Latency (CL)
M6 M5 M4
Reserved
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Burst length is defined by bits M0–M2, as shown in Figure 5. Read
and write accesses to the DDR2 SDRAM are burst-oriented, with
the burst length being programmable to either four or eight. The
burst length determines the maximum number of column locations
that can be accessed for a given READ or WRITE command.
Reserved
Reserved
Mode Register Definition
Mode Register (MR)
M15 M14
3
4
5
6
7
0
1
0
1
0
0
1
1
Extended Mode Register (EMR)
Extended Mode Register (EMR2)
Extended Mode Register (EMR3)
When a READ or WRITE command is issued, a block of columns
equal to the burst length is effectively selected. All accesses for
that burst take place within this block, meaning that the burst
will wrap within the block if a boundary is reached. The block is
uniquely selected by A2–Ai when BL = 4 and by A3–Ai when BL =
8 (where Ai is the most significant column address bit for a given
configuration). The remaining (least significant) address bit(s)
is (are) used to select the starting location within the block. The
programmed burst length applies to both READ and WRITE bursts.
NOTE: Not all listed CL options are supported in any individual speed grades.
BURST TYPE
Accesses within a given burst may be programmed to be either
sequential or interleaved. The burst type is selected via bit M3,
as shown in Figure 5. The ordering of accesses within a burst is
determined by the burst length, the burst type, and the starting
column address, as shown in Table 2. DDR2 SDRAM supports
4-bit burst mode and 8-bit burst mode only. For 8-bit burst mode,
full interleaved address ordering is supported; however, sequential
address ordering is nibble-based.
7
4163.12E-0716-ss-W3H128M72E-XSBX / XNBX
Mercury Corp. - Memory and Storage Solutions • (602) 437-1520 • www.mrcy.com
MERCURY [ MERCURY UNITED ELECTRONICS INC ]
