W3E32M64S-XBX
White Electronic Designs
detect an LVCMOS LOW level after VCC is applied.After CKE
passes through VIH, it will transition to an SSTL_2 signal
and remain as such until power is cycled. Maintaining an
LVCMOS LOW level on CKE during power-up is required
to ensure that the DQ and DQS outputs will be in the
High-Z state, where they will remain until driven in normal
operation (by a read access). After all power supply and
reference voltages are stable, and the clock is stable, the
DDR SDRAM requires a 200μs delay prior to applying an
executable command.
FIGURE 2 – FUNCTIONAL BLOCK DIAGRAM
WE0#
RAS
0
#
#
CAS
0
WE# RAS# CAS#
VREF
A
0-12
A
0-12
DQ
0
DQ
0
BA0-1
CLK
CLK#
CKE
CS#
DQML
DQMH
DQSL
DQSH
BA0-1
=
=
Y
Y
CLK
CLK
CKE
CS
0
=
=
Y
Y
0
#
0
=
=
Y
Y
U0
=
=
Y
Y
0
#
=
=
Y
Y
=
=
Y
Y
DQML
DQMH
DQSL
DQSH
0
0
0
0
Once the 200μs delay has been satisfied, a DESELECT
or NOP command should be applied, and CKE should
be brought HIGH. Following the NOP command, a
PRECHARGE ALL command should be applied. Next a
LOAD MODE REGISTER command should be issued for
the extended mode register (BA1 LOW and BA0 HIGH)
to enable the DLL, followed by another LOAD MODE
REGISTER command to the mode register (BA0/BA1
both LOW) to reset the DLL and to program the operating
parameters. Two-hundred clock cycles are required
between the DLL reset and any READ command. A
PRECHARGE ALL command should then be applied,
placing the device in the all banks idle state.
DQ15
DQ15
WE1#
RAS
1
#
#
CAS
1
WE# RAS# CAS#
V
REF
A
0-12
DQ
0
DQ16
BA0-1
CLK
CLK#
=
=
Y
Y
CLK
CLK
CKE
CS
DQML
DQMH
DQSL
DQSH
1
#
=
=
Y
Y
1
=
=
Y
Y
U1
1
CKE
=
=
Y
Y
1
#
CS#
=
=
Y
DQ31
=
Y
Y
=
Y
1
1
1
1
DQML
DQMH
DQSL
DQSH
DQ15
WE2#
RAS
2
#
#
Once in the idle state, two AUTO REFRESH cycles must
be performed (tRFC must be satisfied.)Additionally, a LOAD
MODE REGISTER command for the mode register with
the reset DLL bit deactivated (i.e., to program operating
parameters without resetting the DLL) is required.
Following these requirements, the DDR SDRAM is ready
for normal operation.
CAS
2
WE# RAS# CAS#
REF
V
A0-12
DQ
0
DQ32
BA0-1
CLK
CLK#
CKE
CS#
DQML
DQMH
DQSL
DQSH
=
=
Y
Y
CLK
2
=
=
Y
Y
CLK
CKE
CS
2
#
2
=
=
Y
Y
U2
=
=
Y
Y
=
2
#
=
Y
Y
=
Y
=
Y
DQML
DQMH
2
DQ15
DQ47
2
DQSL
DQSH
2
2
WE3#
RAS
3
#
#
CAS
3
WE# RAS# CAS#
REF
V
A0-12
DQ
0
DQ48
BA0-1
CLK
CLK#
CKE
CS#
DQML
DQMH
DQSL
DQSH
=
=
Y
Y
CLK
CLK
CKE
CS
DQML
DQMH
DQSL
DQSH
3
=
=
Y
Y
3
#
3
=
=
Y
Y
U3
=
=
Y
Y
=
=
Y
Y
3
#
=
Y
=
Y
3
3
3
3
DQ15
DQ63
February 2007
Rev. 4
4
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
MERCURY [ MERCURY UNITED ELECTRONICS INC ]
