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W3E32M64S-333BI 参数 Datasheet PDF下载

W3E32M64S-333BI图片预览
型号: W3E32M64S-333BI
PDF下载: 下载PDF文件 查看货源
内容描述: [DDR DRAM, 32MX64, 0.7ns, CMOS, PBGA219, 25 X 25 MM, PLASTIC, BGA-219]
分类和应用: 时钟动态存储器双倍数据速率内存集成电路
文件页数/大小: 17 页 / 847 K
品牌: MERCURY [ MERCURY UNITED ELECTRONICS INC ]
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W3E32M64S-XBX  
White Electronic Designs  
TRUTH TABLE – COMMANDS (NOTE 1)  
NAME (FUNCTION)  
CS#  
H
L
RAS#  
CAS#  
WE#  
X
ADDR  
X
DESELECT (NOP) (9)  
X
H
L
X
H
H
L
NO OPERATION (NOP) (9)  
H
X
ACTIVE (Select bank and activate row) (3)  
READ (Select bank and column, and start READ burst) (4)  
WRITE (Select bank and column, and start WRITE burst) (4)  
BURST TERMINATE (8)  
L
H
Bank/Row  
Bank/Col  
Bank/Col  
X
L
H
H
H
L
H
L
L
L
L
H
H
L
L
PRECHARGE (Deactivate row in bank or banks) ( 5)  
AUTO REFRESH or SELF REFRESH (Enter self refresh mode) (6, 7)  
LOAD MODE REGISTER (2)  
L
L
Code  
X
L
L
H
L
L
L
L
Op-Code  
TRUTH TABLE – DM OPERATION  
NAME (FUNCTION)  
WRITE ENABLE (10)  
WRITE INHIBIT (10)  
DM  
L
DQs  
Valid  
X
H
NOTES:  
1. CKE is HIGH for all commands shown except SELF REFRESH.  
2. A0-12 dene the op-code to be written to the selected Mode Register. BA0, BA1  
select either the mode register (0, 0) or the extended mode register (1, 0).  
3. A0-12 provide row address, and BA0, BA1 provide bank address.  
4. A0-8 provide column address; A10 HIGH enables the auto precharge feature (non  
persistent), while A10 LOW disables the auto precharge feature; BA0, BA1 provide  
bank address.  
6. This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is  
LOW.  
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care”  
except for CKE.  
8. Applies only to read bursts with auto precharge disabled; this command is undened  
(and should not be used) for READ bursts with auto precharge enabled and for  
WRITE bursts.  
5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks  
precharged and BA0, BA1 are “Don’t Care.”  
9. DESELECT and NOP are functionally interchangeable.  
10. Used to mask write data; provided coincident with the corresponding data.  
between any AUTO REFRESH command and the next  
AUTO REFRESH command is 9 x 7.8125μs (70.3μs). This  
maximum absolute interval is to allow future support for  
DLL updates internal to the DDR SDRAM to be restricted  
to AUTO REFRESH cycles, without allowing excessive  
drift in tAC between updates.  
AUTO REFRESH  
AUTO REFRESH is used during normal operation of the  
DDR SDRAM and is analogous to CAS-BEFORE-RAS  
(CBR) REFRESH in conventional DRAMs. This command  
is non persistent, so it must be issued each time a refresh  
is required.  
Although not a JEDEC requirement, to provide for future  
functionality features, CKE must be active (High) during  
theAUTO REFRESH period. TheAUTO REFRESH period  
begins when theAUTO REFRESH command is registered  
and ends tRFC later.  
The addressing is generated by the internal refresh  
controller. This makes the address bits “Don’t Care” during  
an AUTO REFRESH command. Each DDR SDRAM  
requires AUTO REFRESH cycles at an average interval  
of 7.8125μs (maximum).  
To allow for improved efficiency in scheduling and  
switching between tasks, some exibility in the absolute  
refresh interval is provided. A maximum of eight AUTO  
REFRESH commands can be posted to any given DDR  
SDRAM, meaning that the maximum absolute interval  
SELF REFRESH*  
The SELF REFRESH command can be used to retain  
data in the DDR SDRAM, even if the rest of the system is  
powered down. When in the self refresh mode, the DDR  
SDRAM retains data without external clocking. The SELF  
February 2007  
Rev. 4  
9
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com