EDI88130CS
FIGURE 2 – TIMING WAVEFORM – READ CYCLES
tAVAV
ADDRESS
CS1#
tAVQV
tAVAV
tE1LQV
tE1HQZ
tE1LQX
ADDRESS
DATA I/O
ADDRESS 1
ADDRESS 2
tE1HICCL
tE1LICCH
Icc
tE2LICCL
tE2HQV
tAVQV
tAVQX
CS2
tE2HICCH
DATA 1
DATA 2
tE2HQX
OE#
READ CYCLE 1 (WE# HIGH; OE#, CS# LOW)
tGLQV
tGLQX
tGHQZ
DATA I/O
READ CYCLE 2 (CS1# AND/OR CS2 CONTROLLED, WE# HIGH)
FIGURE 3 – WRITE CYCLE 1
tAVAV
ADDRESS
tAVWH
tAVWL
tWHAX
tWLWH
WE#
CS1#
CS2
tE1LWH
tE2HWH
tDVWH
tWHDX
DATA IN
tWLQZ
tWHQX
DATA OUT
WRITE CYCLE 1 - LATE WRITE, WE# CONTROLLED
FIGURE 4 –
WRITE CYCLES 2
WRITE CYCLES 3
tAVAV
tAVAV
ADDRESS
ADDRESS
tAVE2H
tAVE1L
tE2HE2L
tE2LAX
tE1LE1H
tE1HAX
WE#
CS1#
CS2
WE#
CS1#
CS2
tDVE2L
tE2LDX
tDVE1H
tE1HDX
DATA I/O
DATA I/O
WRITE CYCLE 3 – EARLY WRITE, CS2 CONTROLLED
WRITE CYCLE 2 – EARLY WRITE, CS1# CONTROLLED
5
4248.15E-0816-ss-EDI88130CS
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