19.3 Interrupt Enable
Each of these interrupt sources can be individually enabled or disabled by setting or clearing an interrupt enable
bit in the registers IE, AUXIE and XICON. Note that IE also contains a global disable bit, EA. If EA is set to ‘1’, the
interrupts are individually enabled or disabled by their corresponding enable bits. If EA is cleared to ‘0’, all
interrupts are disabled.
19.4 Interrupt Priority
The priority scheme for servicing the interrupts is the same as that for the 80C51, except there are four interrupt
levels rather than two as on the 80C51. The Priority Bits (see Table 19-1) determine the priority level of each
interrupt. Table 19-2, as an illustration example using External Interrupt 0, shows the bit values and priority levels
associated with each combination.
Table 19-2. Four Priority Level of External Interrupt 0
Priority Bits
PX0H
Priority Level
PX0
0
0
0
1
1
Level 0 (Lowest)
Level 1
1
0
Level 2
1
Level 3 (Highest)
An interrupt will be serviced as long as an interrupt of equal or higher priority is not already being serviced. If an
interrupt of equal or higher level priority is being serviced, it won’t be stopped and the new interrupt will wait until
it is finished. If a lower priority level interrupt is being serviced, it will be stopped and the new interrupt will be
serviced immediately. When the new interrupt is finished, the lower priority level interrupt that was stopped will be
completed. In other words, a priority interrupt can itself be interrupted by a higher priority interrupt, but not by
another equal or lower priority interrupt.
If two requests of different priority levels are received simultaneously, the request of higher priority level is
serviced. If requests of the same priority level are received simultaneously, the “Priority within Level” determines
which request is serviced. Thus within each priority level there is a second priority structure determined by the
polling sequence. Note the ‘Priority within Level’ is only used to resolve simultaneous requests of the same
priority level.
19.5 How Interrupts are Handled
The interrupt flags are sampled every instruction cycle. The samples are polled during the following instruction
cycle. If one of the interrupt flags was in a set condition in the preceding cycle, the polling cycle will find it and the
interrupt system will generate an LCALL to the appropriate service routine, provided this hardware-generated
LCALL is not blocked by any of the following conditions:
1. An interrupt of equal or higher priority level is already in progress.
2. The current (polling) cycle is not the final cycle in the execution of the instruction in progress.
3. The instruction in progress is RETI or any write to the registers associated the interrupts.
Any of these three conditions will block the generation of the LCALL to the interrupt service routine. Condition 2
ensures that the instruction in progress will be completed before vectoring to any service routine. Condition 3
ensures that if the instruction in progress is RETI or any write to the registers associated the interrupts, then at
least one more instruction will be executed before any interrupt is vectored to.
The polling cycle is repeated with each instruction cycle, and the values polled are the values that were present
in the previous instruction cycle. If the interrupt flag for a level-sensitive external interrupt is active but not being
responded to for one of the above conditions and is not still active when the blocking condition is removed, the
denied interrupt will not be serviced. In other words, the fact that the interrupt flag was once active but not
serviced is not remembered. Every polling cycle is new.
The processor acknowledges an interrupt request by executing a hardware-generated LCALL to the appropriate
servicing routine. In some cases it also clears the flag that generated the interrupt, and in other cases it doesn’t. It
93
MPC82G516A Data Sheet
MEGAWIN
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