20.2 ISP Operation
In general, the user needn’t know how ISP operates because Megawin has provided the standard ISP tool (see
Section 20.2.5). For the user who wants to design his own ISP operation, this section includes all the necessary
technical information for ISP.
20.2.1 SFRs for ISP
The following special function registers are related to the ISP operation. All these registers can be accessed by
software in the user’s application program.
ISPCR (Address=E7H, ISP Control Register, Reset Value=000x,x000B)
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
ISPEN
SWBS SWRST
-
-
CKS2
CKS1
CKS0
ISPEN: Set to enable ISP function.
SWBS: Software boot select. Set/clear to select booting from ISP-memory/AP-memory for software reset.
SWRST: Write ‘1’ to this bit to trigger a software reset.
CKS2~CKS0: Configure ISP timing according to the oscillator frequency, see Table 20-2.
Table 20-2. ISP Timing Setting
CKS2 CKS1 CKS0
Oscillator Frequency (MHz)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
> 24
20 ~ 24
12 ~ 20
6~ 12
3 ~ 6
2 ~ 3
1 ~ 2
< 1
IFMT (Address=E5H, ISP Mode Register, Reset Value=xxxx,x000B)
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
-
-
-
-
-
MS2
MS1
MS0
MS2, MS1 and MS0: ISP mode select bits, see Table 20-3.
Table 20-3. ISP Mode Select
MS2 MS1 MS0
ISP Mode
0
0
0
0
0
0
1
1
0
1
0
1
Standby
Read
Program
Page Erase
Standby Mode: Keep the ISP hardware in the deactivated state
Page Erase Mode: Erase one page (512 bytes) specified by the page address in [IFADRH,IFADRL]
Program Mode: Program data to Flash specified by the byte address in [IFADRH,IFADRL]
Read Mode: Read data from Flash specified by the byte address in [IFADRH,IFADRL]
97
MPC82G516A Data Sheet
MEGAWIN
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