20.3.3 Notes for IAP
Interrupts during IAP
After triggering the ISP processing for In-Application Programming, the MCU will halt for a while for internal ISP
processing until the processing is completed. At this time, the interrupt will queue up for being serviced if the
interrupt is enabled previously. Once the processing is completed, the MCU continues running and the interrupts
in the queue will be serviced immediately if the interrupt flag is still active. Users, however, should be aware of
the following:
(1) Any interrupt can not be in-time serviced during the MCU halts for ISP processing.
(2) The low-level triggered external interrupts, /INTx, should keep activated until the ISP is completed, or they
will be neglected.
Accessing Destination of IAP
As mentioned previously, the IAP is used to program only the IAP-memory. Once the accessing destination is not
within the IAP-memory, the hardware will automatically neglect the triggering of ISP processing. That is the
triggering of ISP is invalid and the hardware does nothing.
An Alternative Method to Read IAP Data
To read the Flash data in the IAP-memory, in addition to using the Flash Read Mode, the alternative method is
using the instruction “MOVC A,@A+DPTR”. Where, DPTR and ACC are filled with the wanted address and the
offset, respectively. And, the accessing destination must be within the IAP-memory, or the read data will be
indeterminate. Note that using ‘MOVC’ instruction is much faster than using the Flash Read Mode.
Flash Endurance for IAP
The endurance of the embedded Flash is 20,000 erase/write cycles, that is to say, the erase-then-write cycles
shouldn’t exceed 20,000 times. Thus the user should pay attention to it in the application which needs to
frequently update the IAP-memory.
Flash Write Protection during Low Power
To ensure a successful programming using IAP, the power coming from LDO output and supplied to the Flash
memory should be higher than 2.4V (see Figure 23-1). The user may enable the hardware option LVFWP for
write protection during the LDO output power falls below 2.4V during ISP processing. Refer to Section 25: MCU’s
Hardware Option.
109
MPC82G516A Data Sheet
MEGAWIN
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