MG87FE/L2051/4051/6051
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Preliminary Ver 1.00
Bit 7: PX3H/PTCH, external interrupt 3 priority-H register. It has an alternate function for PWM-Timer interrupt
priority-H register when CMOD.ECF is enabled.
Bit 6: PX2H/PACH, external interrupt 2 priority-H register. It has an alternate function for Analog Comparator
interrupt priority-H register when IE.EAC is enabled.
Bit 5: Reserved.
Bit 4: PSH, Serial port interrupt priority-H register.
Bit 3: PT1H, Timer 1 interrupt priority-H register.
Bit 2: PX1H, external interrupt 1 priority-H register.
Bit 1: PT0H, Timer 0 interrupt priority-H register.
Bit 2: PX0H, external interrupt 0 priority-H register.
IPL (or XICON) and IPH are combined to form 4-level priority interrupt as the following table.
{IPH.x , IPL.x}
Priority Level
1 (highest)
11
10
01
00
2
3
4
There are seven interrupt sources available in MG87FE/L2051/4051/6051. Each interrupt source can be
individually enabled or disabled by setting or clearing a bit in the SFR named IE. This register also contains a
global disable bit(EA), which can be cleared to disable all interrupts at once.
Each interrupt source has two corresponding bits to represent its priority. One is located in SFR named IPH and
the other in IPL (or XICON) register. Higher-priority interrupt will be not interrupted by lower-priority interrupt
request. If two interrupt requests of different priority levels are received simultaneously, the request of higher
priority is serviced. If interrupt requests of the same priority level are received simultaneously, an internal polling
sequence determine which request is serviced. The following table shows the internal polling sequence in the
same priority level and the interrupt vector address.
Source
External interrupt 0
Vector address
03H
Priority within level
(highest)
1
Timer 0
0BH
2
External interrupt 1
Timer1
Serial Port
-
13H
1BH
23H
2BH
3
4
5
-
External interrupt 2 or Comparator
External interrupt 3 or PWM-Timer
33H
3BH
6
7
The external interrupt /INT0, /INT1, /INT2 and /INT3 can each be either level-activated or transition-activated,
depending on bits IT0 and IT1 in register TCON, IT2 and IT3 in register XICON. The flags that actually generate
these interrupts are bits IE0 and IE1 in TCON, IE2 and IE3 in XICON. When an external interrupt is generated,
the flag that generated it is cleared by the hardware when the service routine is vectored to only if the interrupt
was transition –activated, then the external requesting source is what controls the request flag, rather than the
on-chip hardware.
The Timer0 and Timer1 interrupts are generated by TF0 and TF1, which are set by a rollover in their respective
Timer/Counter registers in most cases. When a timer interrupt is generated, the flag that generated it is cleared
by the on-chip hardware when the service routine is vectored to.
The serial port interrupt is generated by the logical OR of RI and TI. Neither of these flags is cleared by hardware
This document information is the intellectual property of Megawin Technology.
© Megawin Technology Co., Ltd. 2009 All rights reserved.
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