MG87FE/L2051/4051/6051
Preliminary, v 1.03
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1: Higher priority, setting with PTCH to select priority level.
Bit 6: EX3, external interrupt 3 enable register.
0: Disable external /INT3.
1: Enable external /INT3. This function will be masked when CMOD.ECF is enabled.
Bit 5: IE3, Interrupt 3 Edge flag.
0: Cleared when interrupt start to be serviced. It also could be cleared by CPU.
1: Set by hardware when external interrupt edge detected. It also could be set by CPU.
Bit 4: IT3, Interrupt 3 type control bit.
0: Cleared by CPU to specify low level triggered on Interrupt 3. If AUXR.INT3H is set, this bit specifies high level
triggered on /INT3.
1: Set by CPU to specify falling edge triggered on Interrupt 3. If AUXR.INT3H is set, this bit specifies rising edge
triggered on /INT3.
Bit 3: PX2, External interrupt 2 priority-L register.
0: Lower priority, setting with PX2H to select priority level.
1: Higher priority, setting with PX2H to select priority level.
Bit 2: EX2, external interrupt 2 enable register.
0: Disable external interrupt 2.
1: Enable external interrupt 2. This function will be masked when IE.EAC is enabled.
Bit 1: IE2, Interrupt 2 Edge flag.
0: Cleared when interrupt start to be serviced. It also could be cleared by CPU.
1: Set by hardware when external interrupt edge detected. It also could be set by CPU.
Bit 0: IT2, Interrupt 2 type control bit.
0: Cleared by CPU to specify low level triggered on /INT2. If AUXR.INT2H is set, this bit specifies high level
triggered on /INT2.
1: Set by CPU to specify falling edge triggered on /INT2. If AUXR.INT2H is set, this bit specifies rising edge
triggered on /INT2.
IPL: Interrupt Priority Low Register
Address=B8H, read/write, Power On + RESET=X0X0-0000
7
-
6
PAC
5
--
4
PS
3
PT1
2
PX1
1
PT0
0
PX0
Bit 7: reserved.
Bit 6: PAC, Analog Comparator interrupt priority-L register.
Bit 5: Reserved.
Bit 4: PS, Serial port interrupt priority-L register.
Bit 3: PT1, Timer 1 interrupt priority-L register.
Bit 2: PX1, external interrupt 1 priority-L register.
Bit 1: PT0, Timer 0 interrupt priority-L register.
Bit 2: PX0, external interrupt 0 priority-L register.
IPH: Interrupt Priority High Register
Address=B7H, read/write, Power On + RESET=00X0-0000
7
6
5
4
3
2
1
0
PX3H/PTCH PX2H/PACH
--
PSH
PT1H
PX1H
PT0H
PX0H
This document information is the intellectual property of Megawin Technology.
© Megawin Technology Co., Ltd. 2009 All rights reserved.
QP-7300-03D
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