Megawin Technology Co., Ltd.
MG87FE/L52
level are received simultaneously, an internal polling sequence determine which request is
serviced. The following table shows the internal polling sequence in the same priority level and
the interrupt vector address.
Source
External interrupt 0
Timer 0
Vector address
03H
Priority within level
1
2
3
4
5
6
7
8
(highest)
0BH
External interrupt 1
Timer1
13H
1BH
Serial Port
23H
Timer2
2BH
External interrupt 2
External interrupt 3
33H
3BH
The external interrupt /INT0, /INT1, /INT2 and /INT3 can each be either level-activated or
transition-activated, depending on bits IT0 and IT1 in register TCON, IT2 and IT3 and XICON.
The flags that actually generate these interrupts are bits IE0 and IE1 in TCON, IE2 and IE3 in
XICON. When an external interrupt is generated, the flag that generated it is cleared by the
hardware when the service routine is vectored to only if the interrupt was transition –activated,
then the external requesting source is what controls the request flag, rather than the on-chip
hardware.
The Timer0 and Timer1 interrupts are generated by TF0 and TF1, which are set by a rollover in
their respective Timer/Counter registers in most cases. When a timer interrupt was generated,
the flag that generated & it was cleared by the on-chip hardware when the service routine is
vectored to.
The serial port interrupt is generated by the logical OR of RI and TI. Neither of these flags is
cleared by hardware when the service routine is vectored to. The service routine should check
RI and TI to determine which one request service and it will be cleared by software.
The timer2 interrupt is generated by the logical OR of TF2 and EXF2. Just the same as serial
port, neither of these flags is cleared by hardware when the service routine is vectored to.
All of the bits that generate interrupts can be set or cleared by software, with the same result as
though it had been set or cleared by hardware. In other words, interrupts can be generated or
pending interrupts can be canceled in software.
31
Preliminary ver 1.3
Date: 2009-JAN-20
MEGAWIN [ MEGAWIN TECHNOLOGY CO., LTD ]
