Megawin Technology Co., Ltd.
MG87FE/L52
PT0H
PX0H
If set, Set priority for timer0 interrupt highest
If set, Set priority for external interrupt 0 highest
IPL (or XICON) and IPH are combined to form 4-level priority interrupt as the following table.
(IPH.x, IPL.x)
Priority Level
1 (highest)
1,1
1,0
0,1
0,0
2
3
4
External Interrupt Control (XICON) register
Name
Bit7
PX3
Bit6
EX3
Bit5
IE3
Bit4
IT3
Bit3
PX2
Bit2
EX2
Bit1
IE2
Bit0
IT2
XICON
PX3
EX3
If set, Set priority for external interrupt 3 higher.
If set, Enables external interrupt 3.
Interrupt 3 Edge flag. Sets by hardware when external interrupt edge detected.
Cleared when interrupt processed.
IE3
IT3
Interrupt 3 type control bits. Set/Cleared by software to specified falling edge/low
level triggered interrupt.
PX2
EX2
If set, Set priority for external interrupt 3 higher.
If set, enables external interrupt 2.
Interrupt 2 Edge flag. Sets by hardware when external interrupt edge detected.
Cleared when interrupt processed.
IE2
IT2
Interrupt 2 types control bits. Set/Cleared by software to specify falling edge/low
level triggered interrupt.
There are eight interrupt sources available in MG87FE/L52. Each interrupt source can be
individually enabled or disabled by setting or clearing a bit in the SFR named IE. This register
also contains a global disable bit(EA), which can be cleared to disable all interrupts at once.
Each interrupt source has two corresponding bits to represent its priority. One is located in SFR
named IPH and the other in IPL register. Higher-priority interrupt will be not interrupted by
lower-priority interrupt request. If two interrupt requests of different priority levels are received
simultaneously, the request of higher priority is serviced. If interrupt requests of the same priority
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Preliminary ver 1.3
Date: 2009-JAN-20
MEGAWIN [ MEGAWIN TECHNOLOGY CO., LTD ]
