MG87FE/L2051/4051/6051
MAKE YOU WIN
Preliminary Ver 1.00
10.1.5. Timer0/1 Register
TMOD: Timer/Counter Mode Control Register
Address=89H, read/write, Power On + RESET=0000-0000
7
6
5
4
3
2
1
0
GATE
C/T
M1
M0
GATE
C/T
M1
M0
|Å----------------------- Timer1 -------------------------Æ|Å--------------------------Timer0 ------------------------Æ|
Bit 7/3: Gate, Gating control for Timer1/0.
0: Disable gating control for Timer1/0.
1: Enable gating control for Timer1/0. When set, Timer1/0 or Counter1/0 is enabled only when /INT1 or /INT0 pin
is high and TR1 or TR0 control bit is set.
Bit 6/2: C/T, Timer for Counter function selector.
0: Clear for Timer operation, input from internal system clock.
1: Set for Counter operation, input form T1 input pin.
Bit 5~4/1~0: Operating mode selection.
M1
0
0
M0
0
1
Operating Mode
13-bit timer/counter for Timer0 and Timer1
16-bit timer/counter for Timer0 and Timer1
8-bit timer/counter with automatic reload for Timer0 and Timer1
1
0
1
1
1 (Timer0) TL0 is 8-bit timer/counter, TH0 is locked into 8-bit timer
1 (Timer1) Timer/Counter1 Stopped
TCON: Timer/Counter Control Register
Address=88H, read/write, Power On + RESET=0000-0000
7
6
5
4
3
2
1
0
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Bit 7: TF1, Timer 1 overflow flag.
0: Cleared by hardware when the processor vectors to the interrupt routine, or cleared by software.
1: Set by hardware on Timer/Counter 1 overflow, or set by software.
Bit 6: TR1, Timer 1 Run control bit.
0: Cleared by software to turn Timer/Counter 1 off.
1: Set by software to turn Timer/Counter 1 on.
Bit 5: TF0, Timer 0 overflow flag.
0: Cleared by hardware when the processor vectors to the interrupt routine, or cleared by software.
1: Set by hardware on Timer/Counter 0 overflow, or set by software.
Bit 4: TR0, Timer 0 Run control bit.
0: Cleared by software to turn Timer/Counter 0 off.
1: Set by software to turn Timer/Counter 0 on.
Bit 3: IE1, Interrupt 1 Edge flag.
0: Cleared when interrupt processed on if transition-activated.
1: Set by hardware when external interrupt 1 edge is detected (transmitted or level-activated).
Bit 2: IT1: Interrupt 1 Type control bit.
0: Cleared by software to specify low level triggered external interrupt 1.
This document information is the intellectual property of Megawin Technology.
© Megawin Technology Co., Ltd. 2009 All rights reserved.
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