MG87FE/L2051/4051/6051
Preliminary, v 1.03
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10.1.3. Mode 2 Structure
Mode 2 configures the timer register as an 8-bit counter(TLx) with automatic reload. Overflow from TLx not only
set TFx, but also reload TLx with the content of THx, which is determined by software. The reload leaves THx
unchanged. Mode 2 operation is the same for Timer0 and Timer1.
SYSCLK
Tx Pin
12
C//T=0
C//T=1
Overflow
TLx[7:0]
THx[7:0]
TFx
Interrupt
Reload
TRx
x = 0 or 1
GATE
/INTx Pin
10.1.4. Mode 3 Structure
Timer1 in Mode3 simply holds its count, the effect is the same as setting TR1 = 1. Timer0 in Mode 3 enables TL0
and TH0 as two separate 8-bit counters. TL0 uses the Timer0 control bits such like C/T, GATE, TR0, INT0 and
TF0. TH0 is locked into a timer function (can not be external event counter) and take over the use of TR1, TF1
from Timer1. TH0 now controls the Timer1 interrupt.
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© Megawin Technology Co., Ltd. 2009 All rights reserved.
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