MG87FE/L2051/4051/6051
MAKE YOU WIN
Preliminary Ver 1.00
exited, the oscillator is restarted, and an internal timer begins counting. The internal clock will not be allowed to
propagate and the CPU will not resume execution until after the timer has reached internal counter full. After the
timeout period, the interrupt service routine will begin. To prevent the interrupt from re-triggering, the ISR should
disable the interrupt before returning. The interrupt pin should be held low until the device has timed out and
begun executing.
When PWDEX = 1 the wake-up period is controlled externally by the interrupt. Again, at the falling edge on the
interrupt pin, Power-down is exited and the oscillator is restarted. However, the internal clock will not propagate
and CPU will not resume execution until the rising edge of the interrupt pin. After the rising edge on the pin, the
interrupt service routine will begin. The interrupt should be held low long enough for the oscillator to stabilize.
15.1.4. Reset Recovery from Power-down
Wake-up from Power-down through an external reset is similar to the interrupt with PWDEX = 0. At the rising
edge of RST, Power-down is exited, the oscillator is restarted, and an internal timer begins counting. The internal
clock will not be allowed to propagate to the CPU until after the timer has reached internal counter full. The RST
pin must be held high for longer than the timeout period to ensure that the device is reset properly. The device will
begin executing once RST is brought low.
It should be noted that when idle is terminated by a hardware reset, the device normally resumes program
execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control.
On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To
eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction
following the one that invokes Idle should not be one that writes to a port pin or to external memory.
15.1.5. GPIO wake-up Recovery from Power-down
The GPIOs of MG87FE/L2051/4051/6051, P1.7 ~ P1.0 and P3.0 ~ P3.5, P3.7 have wake-up CPU capability that
are enabled by individual control bit in P1WKPE and P3WKPE. If the interrupt is disabled on P3.2/INT0 or
P3.3/INT1, P3.2 and P3.3 still have the wake-up function from the P3WKPE control. But P4.2/INT3 and
P4.3/INT2 can wake-up CPU only when the respective interrupt is enabled.
Wake-up from Power-down through an enabled wake-up GPIO is similar to the interrupt with PWDEX = 0. At the
falling edge of enabled wake-up GPIO, Power-down is exited, the oscillator is restarted, and an internal timer
begins counting. The internal clock will not be allowed to propagate to the CPU until after the timer has reached
internal counter full. After the timeout period, there is no any interrupt and CPU will execute the following
command after last power-down instruction. That is, the enabled wake-up GPIOs will only have the capability to
wake-up CPU without any interrupt function.
15.2. Power Control Register
PCON: Power Control Register
Address=87H, read/write, Power On + RESET =0001-0000, RESET=000x-0000
7
6
5
4
3
2
1
0
SMOD
SMOD0
PWMEN
POF
GF1
GF0
PD
IDL
Bit 7: SMOD, double Baud rate control bit.
0: Disable double Baud rate of the UART.
1: Enable double Baud rate of the UART in mode 1, 2, or 3.
This document information is the intellectual property of Megawin Technology.
© Megawin Technology Co., Ltd. 2009 All rights reserved.
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