MG87FE/L2051/4051/6051
Preliminary, v 1.03
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15. Power Management
MG87FE/L2051/4051/6051 supports two power-reducing modes: Idle and Power-down mode. These two modes
are accessed through the PCON register.
15.1. Power Saving Mode
15.1.1. Idle Mode
Setting the IDL bit in PCON enters idle mode. Idle mode halts the internal CPU clock. The CPU state is preserved
in its entirety, including the RAM, stack pointer, program counter, program status word, and accumulator. The
Port pins hold the logical states they had at the time that Idle was activated. Idle mode leaves the peripherals
running in order to allow them to wake up the CPU when an interrupt is generated. Timer 0, Timer 1, PWM-Timer
and the UART will continue to function during Idle-mode. The analog comparator is disabled during Idle. Any
enabled interrupt source or reset may terminate Idle-mode. When exiting Idle-mode with an interrupt, the
interrupt will immediately be serviced, and following RETI, the next instruction to be executed will be the one
following the instruction that put the device into Idle.
P1.0 and P1.1 should be set to “0” if no external pull-ups are used, or set to “1” if external pull-ups are used, or
set to “1” if AUXR.P10PU&P11PU are enabled.
15.1.2. Power-down Mode
Setting the PD bit in PCON enters Power-down mode. Power-down mode stops the oscillator and powers down
the Flash memory in order to minimize power consumption. Only the power-on circuitry will continue to draw
power during Power-down. During Power-down the power supply voltage may be reduced to the RAM keep-alive
voltage. The RAM contents will be retained; however, the SFR contents are not guaranteed once VDD has been
reduced. Power-down may be exited by external reset, power-on reset, enabled external interrupts, or enabled
wake-up GPIOs.
The user should not attempt to enter (or re-enter) the power-down mode for a minimum of 4 μs until after one of
the following conditions has occurred: Start of code execution (after any type of reset), or exit from power-down
mode.
15.1.3. Interrupt Recovery from Power-down
Four external interrupts may be configured to terminate Power-down mode. External interrupts /INT0 (P3.2),
/INT1 (P3.3), /INT2 (P4.3) and /INT2 (P4.2) may be used to exit Power-down. To wake up by external interrupt
/INT0, /INT1, /INT2, or /INT3, the interrupt must be enabled and configured for level-sensitive operation.
If the interrupt vector of /INT2 (P4.3) is occupied by Analog Comparator, low level P4.3 input still have wake-up
capability when /INT2 interrupt enable, XICON.EX2, is set (enabled). If the interrupt vector of /INT3 (P4.2) is
occupied by PWM-Timer underflow, low level P4.2 input still have wake-up capability when /INT3 interrupt enable,
XICON.EX3, is set (enabled).
When terminating Power-down by an interrupt, two different wake-up modes are available. When PWDEX in
CKCON3.2 is zero, the wake up period is internally timed. At the falling edge on the interrupt pin, Power-down is
This document information is the intellectual property of Megawin Technology.
© Megawin Technology Co., Ltd. 2009 All rights reserved.
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