MX29LV040C
AUTOMATIC SECTOR ERASE TIMING WAVEFORM
Sector indicated by A13 to A18 are erased. External
erase verify is not required because data are verified
automatically by internal control circuit. Erasure comple-
tion can be verified by Data# Polling and toggle bit check-
ing after automatic erase starts. Device outputs 0 dur-
ing erasure and 1 after erasure on Q7.(Q6 is for toggle
bit; see toggle bit, Data# Polling, timing waveform)
Figure 10. AUTOMATIC SECTOR ERASE TIMING WAVEFORM
Erase Command Sequence(last two cycle)
Read Status Data
VA
tWC
tAS
Sector
Sector
Sector
VA
2AAh
Address
CE#
Address 0
Address 1
Address n
tAH
tCH
tGHWL
OE#
tBAL
tWHWH2
tWP
WE#
Data
tCS
tWPH
tDS tDH
In
Progress
55h
30h
30h
30h
Complete
tVCS
VCC
NOTES:
SA=sector address(for Sector Erase), VA=Valid Address for reading status data(see "Write Operation Status").
P/N:PM1149
REV. 1.3, APR. 24, 2006
30
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