MX29LV040C
REQUIREMENTS FOR READING ARRAY
DATA
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output control
and gates array data to the output pins. WE# should remain
at VIH.
The internal state machine is set for reading array data
upon device power-up. This ensures that no spurious
alteration of the memory content occurs during the power
transition. No command is necessary in this mode to
obtain array data. Standard microprocessor read cycles
that assert valid address on the device address inputs
produce valid data on the device data outputs. The device
remains enabled for read access until the command
register contents are altered.
STANDBY MODE
When the system is not reading or writing to the device,
it can place the device in the standby mode. In this mode,
current consumption is greatly reduced, and the outputs
are placed in the high impedance state, independent of
the OE# input.
The device enters the CMOS standby mode when the
CE# pin is both held at VCC±0.3V. (Note that this is a
more restricted voltage range than VIH.) If CE# is held at
VIH, but not within VCC±0.3V, the device will be in the
standby mode, but the standby current will be greater.
The device requires standard access time (tCE) for read
access when the device is in either of these standby
modes, before it is ready to read data.
If the device is deselected during erasure or program-
ming, the device draws active current until the operation
is completed.
ICC3 in the DC Characteristics table represents the
standby current specification.
WRITE COMMANDS/COMMAND SEQUENCES
To program data to the device or erase sectors of memory
, the system must drive WE# and CE# to VIL, and OE#
to VIH.
An erase operation can erase one sector, multiple sectors
, or the entire device. Table 1 indicates the address space
that each sector occupies. A "sector address" consists
of the address bits required to uniquely select a sector.
The "Writing specific address and data commands or
sequences into the command register initiates device
operations. Table 3 defines the valid register command
sequences. Writing incorrect address and data values or
writing them in the improper sequence resets the device
to reading array data. Section has details on erasing a
sector or the entire chip, or suspending/resuming the erase
operation.
After the system writes the autoselect command
sequence, the device enters the autoselect mode. The
system can then read autoselect codes from the internal
register (which is separate from the memory array) on
Q7-Q0. Standard read cycle timings apply in this mode.
Refer to the Autoselect Mode and Autoselect Command
Sequence section for more information.
ICC2 in the DC Characteristics table represents the active
current specification for the write mode. The "AC
Characteristics" section contains timing specification
table and timing diagrams for write operations.
OUTPUT DISABLE
With the OE# input at a logic high level (VIH), output
from the devices are disabled. This will cause the output
pins to be in a high impedance state.
READ/RESET COMMAND
The read or reset operation is initiated by writing the
read/reset command sequence into the command reg-
ister. Microprocessor read cycles retrieve array data.
The device remains enabled for reads until the command
register contents are altered.
If program-fail or erase-fail happen, the write of F0H will
reset the device to abort the operation. A valid com-
mand must then be written to place the device in the
desired state.
P/N:PM1149
REV. 1.3, APR. 24, 2006
8
MCNIX [ MACRONIX INTERNATIONAL ]
