MX25U4035
MX25U8035
Figure 22. Continously Program (CP) Mode Sequence with Hardware Detection (Command AD)
CS#
20 2122 23 24
0
1
30 31 31 32
47 48
0
7
7
8
0
6
7 8
0
1
6 7 8 9
SCLK
Command
AD (hex)
data in
Byte n-1, Byte n
Valid
Command (1)
data in
Byte 0, Byte1
04 (hex)
05 (hex)
24-bit address
SI
high impedance
status (2)
S0
Note: (1) During CP mode, the valid commands are CP command (AD hex), WRDI command (04 hex), RDSR com-
mand (05 hex), and RDSCUR command (2B hex).
(2) Once an internal programming operation begins, CS# goes low will drive the status on the SO pin and
CS# goes high will return the SO pin to tri-state.
(3) To end the CP mode, either reaching the highest unprotected address or sending Write Disable (WRDI)
command (04 hex) may achieve it and then it is recommended to send RDSCUR command (2B hex) to verify
if CP mode is ended
Figure 23. Sector Erase (SE) Sequence (Command 20)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Command
20
24 Bit Address
SI
7
6
2
1
0
MSB
Note: SE command is 20(hex).
P/N: PM1394
REV. 1.0, MAR. 09, 2009
42
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