MX25U4035
MX25U8035
Table 8. Security Register Definition
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Continuously
Program mode
(CP mode)
LDSO
(indicate if
lock-down
Secrured OTP
indicator bit
x
x
x
x
x
0 = not lock-
down
1 = lock-down
(cannot
program/erase
OTP)
0=normal
Program mode
1=CP mode
(default=0)
0 = non-factory
lock
reserved
reserved
reserved
reserved
reserved
1 = factory
lock
volatile bit volatile bit volatile bit
volatile bit
volatile bit
volatile bit non-volatile bit non-volatile bit
(23) Write Security Register (WRSCUR)
The WRSCUR instruction is for changing the values of Security Register Bits. Unlike write status register, the WREN
instruction is not required before sending WRSCUR instruction. The WRSCUR instruction may change the values
of bit1 (LDSO bit) for customer to lock-down the 512-bit Secured OTP area. Once the LDSO bit is set to "1", the Se-
cured OTP area cannot be updated any more.
The sequence of issuing WRSCUR instruction is :CS# goes low→sending WRSCUR instruction→ CS# goes high.
The CS# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed.
(24) HOLD# pin function enable (HDE)
The HDE instruction is for enabling the HOLD# pin function. The RESET#/HOLD#/SIO# pin defaults to be as RE-
SET# pin function. When HDE instruction is writing to the Flash, and then pin is set to be HOLD# pin. The HOLD
mode will continue until power off. The pin is RESET# pin while power on stage. The HDE instruction is invalid dur-
ing deep power down mode.
P/N: PM1394
REV. 1.0, MAR. 09, 2009
27
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