欢迎访问ic37.com |
会员登录 免费注册
发布采购

MX25L8005M2C-15G 参数 Datasheet PDF下载

MX25L8005M2C-15G图片预览
型号: MX25L8005M2C-15G
PDF下载: 下载PDF文件 查看货源
内容描述: 8M - BIT [ ×1 ] CMOS串行闪存 [8M-BIT [x 1] CMOS SERIAL FLASH]
分类和应用: 闪存存储内存集成电路光电二极管时钟
文件页数/大小: 44 页 / 829 K
品牌: Macronix [ MACRONIX INTERNATIONAL ]
 浏览型号MX25L8005M2C-15G的Datasheet PDF文件第17页浏览型号MX25L8005M2C-15G的Datasheet PDF文件第18页浏览型号MX25L8005M2C-15G的Datasheet PDF文件第19页浏览型号MX25L8005M2C-15G的Datasheet PDF文件第20页浏览型号MX25L8005M2C-15G的Datasheet PDF文件第22页浏览型号MX25L8005M2C-15G的Datasheet PDF文件第23页浏览型号MX25L8005M2C-15G的Datasheet PDF文件第24页浏览型号MX25L8005M2C-15G的Datasheet PDF文件第25页  
MX25L8005  
Table 6. AC CHARACTERISTICS (Temperature = -40°C to 85° C for Industrial grade, Temperature =  
0° C to 70°C for Commercial grade, VCC = 2.7V ~ 3.6V)  
Symbol  
Alt.  
Parameter  
Min.  
Typ. Max.  
Unit  
fSCLK  
fC  
Clock Frequency for the following instructions:  
FAST_READ, PP, SE, BE, CE, DP, RES,RDP  
WREN, WRDI, RDID, RDSR, WRSR  
1KHz  
70 & 86 MHz  
(Condition:15pF)  
66  
MHz  
(Condition:30pF)  
fRSCLK  
tCH(1)  
fR  
Clock Frequency for READ instructions  
1KHz  
7
33  
MHz  
tCLH Clock High Time  
tCLL Clock Low Time  
ns  
ns  
V/ns  
V/ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
us  
us  
us  
ms  
ms  
ms  
s
tCL(1)  
7
tCLCH(2)  
tCHCL(2)  
tSLCH  
tCHSL  
tDVCH  
tCHDX  
tCHSH  
tSHCH  
tSHSL  
Clock Rise Time (3) (peak to peak)  
0.1  
0.1  
5
Clock Fall Time (3) (peak to peak)  
tCSS CS# Active Setup Time (relative to SCLK)  
CS# Not Active Hold Time (relative to SCLK)  
tDSU Data In Setup Time  
5
2
tDH  
Data In Hold Time  
5
CS# Active Hold Time (relative to SCLK)  
CS# Not Active Setup Time (relative to SCLK)  
5
5
tCSH CS# Deselect Time  
100  
tSHQZ(2) tDIS Output Disable Time  
6
8
6
tCLQV  
tV  
Clock Low to Output Valid @33MHz 30pF  
@86MHz/70MHz 15pF or @66MHz 30pF  
0
tCLQX  
tHLCH  
tCHHH  
tHHCH  
tCHHL  
tHO  
Output Hold Time  
HOLD# Setup Time (relative to SCLK)  
HOLD# Hold Time (relative to SCLK)  
HOLD Setup Time (relative to SCLK)  
HOLD Hold Time (relative to SCLK)  
HOLD to Output Low-Z  
5
5
5
5
tHHQX(2) tLZ  
tHLQZ(2) tHZ  
tWHSL(4)  
tSHWL(4)  
tDP(2)  
6
6
HOLD#toOutputHigh-Z  
Write Protect Setup Time  
20  
Write Protect Hold Time  
100  
CS#HightoDeepPower-downMode  
CS# High to Standby Mode without Electronic Signature Read  
CS# High to Standby Mode with Electronic Signature Read  
Write Status Register Cycle Time  
Page Program Cycle Time  
3
3
tRES1(2)  
tRES2(2)  
tW  
1.8  
15  
5
5
1.4  
60  
1
tPP  
tSE  
Sector Erase Cycle Time  
120  
2
tBE  
Block Erase Cycle Time  
tCE  
Chip Erase Cycle Time  
7
15  
s
Note:  
1. tCH + tCL must be greater than or equal to 1/ fC  
2. Value guaranteed by characterization, not 100% tested in production.  
3. Expressed as a slew-rate.  
4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.  
5. Test condition is shown as Figure 3.  
P/N:PM1237  
REV. 2.2, OCT. 23, 2008  
21  
 复制成功!