MX25L8005
Theself-timedPageProgramCycletime(tPP)isinitiatedassoonasChipSelect(CS#)goeshigh. TheWriteinProgress
(WIP) bit still can be check out during the Page Program cycle is in progress. The WIP sets 1 during the tPP timing, and
sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by
BP2, BP1, BP0 bits, the Page Program (PP) instruction will not be executed.
(12) Deep Power-down (DP)
TheDeepPower-down(DP)instructionisforsettingthedeviceontheminimizingthepowerconsumption(toenteringthe
Deep Power-down mode), the standby current is reduced from ISB1 to ISB2). The Deep Power-down mode requires the
Deep Power-down (DP) instruction to enter, during the Deep Power-down mode, the device is not active and all Write/
Program/Eraseinstructionareignored. WhenCS#goeshigh, it'sonlyinstandbymodenotdeeppower-downmode. It's
different from Standby mode.
ThesequenceofissuingDPinstructionis:CS#goeslow->sendingDPinstructioncode->CS#goeshigh.(seeFigure22)
OncetheDPinstructionisset,allinstructionwillbeignoredexcepttheReleasefromDeepPower-downmode(RDP)and
ReadElectronicSignature(RES)instruction.(RESinstructiontoallowtheIDbeenreadout).WhenPower-down,thedeep
power-down mode automatically stops, and when power-up, the device automatically is in standby mode. For RDP
instruction the CS# must go high exactly at the byte boundary (the latest eighth bit of instruction code been latched-in);
otherwise, the instruction will not executed. As soon as Chip Select (CS#) goes high, a delay of tDP is required before
entering the Deep Power-down mode and reducing the current to ISB2.
(13) Release from Deep Power-down (RDP), Read Electronic Signature (RES)
TheReleasefromDeepPower-down(RDP)instructionisterminatedbydrivingChipSelect(CS#)High.WhenChipSelect
(CS#) is driven High, the device is put in the Stand-by Power mode. If the device was not previously in the Deep Power-
downmode,thetransitiontotheStand-byPowermodeisimmediate.IfthedevicewaspreviouslyintheDeepPower-down
mode, though, the transition to the Stand-by Power mode is delayed by tRES2, and Chip Select (CS#) must remain High
for at least tRES2(max), as specified in Table 6. Once in the Stand-by Power mode, the device waits to be selected, so
that it can receive, decode and execute instructions.
RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as table of ID
Definitions. ThisisnotthesameasRDIDinstruction.Itisnotrecommendedtousefornewdesign.Fornewdeisng,please
use RDID instruction. Even in Deep power-down mode, the RDP and RES are also allowed to be executed, only except
the device is in progress of program/erase/write cycle; there's no effect on the current program/erase/write cycle in
progress.
The sequence is shown as Figure 23,24.
The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeatedly if
continuouslysendtheadditionalclockcyclesonSCLKwhileCS#isatlow. IfthedevicewasnotpreviouslyinDeepPower-
downmode,thedevicetransitiontostandbymodeisimmediate. IfthedevicewaspreviouslyinDeepPower-downmode,
there'sadelayoftRES2totransittostandbymode,andCS#mustremaintohighatleasttRES2(max). Onceinthestandby
mode, the device waits to be selected, so it can be receive, decode, and execute instruction.
The RDP instruction is for releasing from Deep Power Down Mode.
P/N:PM1237
REV. 2.2, OCT. 23, 2008
15
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