MX25L4006E
Table 7. AC CHARACTERISTICS (Temperature = -40°C to 85°C, VCC = 2.7V ~ 3.6V)
Symbol
Alt.
Parameter
Min.
Typ.
Max.
Unit
Clock Frequency for the following instructions:
fSCLK
fC FAST_READ, RDSFDP, PP, SE, BE, CE, DP, RES,
RDP, WREN, WRDI, RDID, RDSR, WRSR
DC
86
MHz
fRSCLK
fTSCLK
fR Clock Frequency for READ instructions
fT Clock Frequency for DREAD instructions
DC
DC
13
5.5
13
5.5
0.1
0.1
7
33
80
MHz
MHz
ns
ns
ns
@33MHz
tCH(1)
tCL(1)
tCLH Clock High Time
@86MHz
@33MHz
tCLL Clock Low Time
@86MHz
ns
tCLCH(2)
tCHCL(2)
tSLCH
Clock Rise Time (3) (peak to peak)
Clock Fall Time (3) (peak to peak)
tCSS CS# Active Setup Time (relative to SCLK)
CS# Not Active Hold Time (relative to SCLK)
V/ns
V/ns
ns
tCHSL
7
ns
tDVCH tDSU Data In Setup Time
2
ns
tCHDX
tCHSH
tSHCH
tDH Data In Hold Time
CS# Active Hold Time (relative to SCLK)
5
7
7
ns
ns
ns
CS# Not Active Setup Time (relative to SCLK)
Read
Write
15
40
ns
ns
tSHSL
tCSH CS# Deselect Time
tSHQZ(2) tDIS Output Disable Time
6
8
6
ns
ns
ns
30pF
15pF
tCLQV
tV Clock Low to Output Valid
tCLQX
tHLCH
tCHHH
tHHCH
tCHHL
tHO Output Hold Time
0
5
5
5
5
ns
ns
ns
ns
HOLD# Setup Time (relative to SCLK)
HOLD# Hold Time (relative to SCLK)
HOLD Setup Time (relative to SCLK)
HOLD Hold Time (relative to SCLK)
ns
tHHQX(2) tLZ HOLD to Output Low-Z
tHLQZ(2) tHZ HOLD# to Output High-Z
6
6
ns
ns
tWHSL(4)
tSHWL(4)
tDP(2)
Write Protect Setup Time
Write Protect Hold Time
CS# High to Deep Power-down Mode
20
100
ns
ns
us
10
CS# High to Standby Mode without Electronic
Signature Read
CS# High to Standby Mode with Electronic Signature
Read
tRES1(2)
tRES2(2)
8.8
us
us
8.8
tW
Write Status Register Cycle Time
Byte-Program
Page Program Cycle Time
Sector Erase Cycle Time
Block Erase Cycle Time
5
9
1.4
60
0.7
3.5
40
300
5
300
2
ms
us
ms
ms
s
tBP
tPP
tSE
tBE
tCE
Chip Erase Cycle Time
7.5
s
Note:
1. tCH + tCL must be greater than or equal to 1/f (fC or fR).
2. Value guaranteed by characterization, not 100% tested in production.
3. Expressed as a slew-rate.
4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.
5. Test condition is shown as Figure 5 & 6.
6. The CS# rising time needs to follow tCLCH spec and CS# falling time needs to follow tCHCL spec.
P/N: PM1576
REV. 1.3, FEB. 10, 2012
29
Macronix [ MACRONIX INTERNATIONAL ]
