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MX23J25640TI-50G 参数 Datasheet PDF下载

MX23J25640TI-50G图片预览
型号: MX23J25640TI-50G
PDF下载: 下载PDF文件 查看货源
内容描述: 256M - BIT NAND接口XtraROMTM [256M-BIT NAND INTERFACE XtraROMTM]
分类和应用: 存储内存集成电路光电二极管OTP只读存储器
文件页数/大小: 20 页 / 280 K
品牌: Macronix [ MACRONIX INTERNATIONAL ]
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MX23J25640  
Operation Commands  
The following six operation settings are possible by inputting commands from I/O pins.  
Command  
Hex  
I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 Command receivable  
during Busy  
Read mode(1)  
Read mode(2)  
Read mode(3)Note1  
Reset Note2  
00  
01  
50  
FF  
L
L
L
H
L
L
L
L
H
L
L
L
L
H
L
L
L
H
L
L
L
H
L
L
L
H
L
H
H
H
H
H
Notes:  
1.The data output in read mode (3) is all FFH.  
2. The only command that can be executed when the device is Busy is the reset command. Do not set any of the  
other commands while the device is Busy.  
I/O Pin Correspondence Table during Address Input Cycle (Address Setting)  
(1) When 00H or 01H command is set [Read mode (1), Read mode (2)]  
Command  
I/O7  
A7  
I/O6  
A6  
I/O5  
A5  
I/O4  
A4  
I/O3  
A3  
I/O2  
A2  
I/O1  
A1  
I/O0  
A0  
1st address cycle  
2nd address cycle  
3rd address cycle  
A16  
A24  
A15  
A23  
A14  
A22  
A13  
A21  
A12  
A20  
A11  
A19  
A10  
A18  
A9  
A17  
(2) When 50H command is set [Read mode (3)]  
Command  
I/O7  
X
I/O6  
X
I/O5  
X
I/O4  
X
I/O3  
A3  
I/O2  
A2  
I/O1  
A1  
I/O0  
A0  
1st address cycle  
2nd address cycle  
3rd address cycle  
A16  
A24  
A15  
A23  
A14  
A22  
A13  
A21  
A12  
A20  
A11  
A19  
A10  
A18  
A9  
A17  
Remarks  
1. A0 to A24 are internal addresses.  
2. Internal address A8 is set internally with command 00H or 01H.  
3. When 50H command is set [read mode (3)], the I/O4, I/O5, I/O6, and I/O7 inputs of the 1st address cycle are VIH  
or VIL.  
P/N:PM1137  
REV. 1.2, OCT. 28, 2005  
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